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Searched refs:sw59 (Results 1 – 9 of 9) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_vdpu2_reg.h124 } sw59; member
H A Dhal_avsd_vdpu2.c56 p_regs->sw59.pred_bc_tap_0_0 = 0x3FF; in set_defalut_parameters()
57 p_regs->sw59.pred_bc_tap_0_1 = 5; in set_defalut_parameters()
58 p_regs->sw59.pred_bc_tap_0_2 = 5; in set_defalut_parameters()
H A Dhal_avsd_plus_reg.h278 RK_U32 sw59; member
/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu2_v2.c100 regs->sw59.cabac_enable = hw_cfg->enable_cabac; in vp8e_vpu_frame_start()
103 regs->sw59.disable_qp_mv = hw_cfg->disable_qp_mv; in vp8e_vpu_frame_start()
104 regs->sw59.deblocking = hw_cfg->filter_disable; in vp8e_vpu_frame_start()
H A Dhal_vp8e_vepu1_reg.h300 } sw59; member
H A Dhal_vp8e_vepu2_reg.h228 } sw59; member
H A Dhal_vp8e_vepu1_v2.c199 regs->sw59.base_partition2 = hw_cfg->partition_Base[1]; in vp8e_vpu_frame_start()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu2.c70 p_reg->sw59.pflt_set0_tap0 = 1; in set_device_regs()
72 p_reg->sw59.pflt_set0_tap1 = val; in set_device_regs()
73 p_reg->sw59.pflt_set0_tap2 = 20; in set_device_regs()
H A Dhal_h264d_vdpu2_reg.h132 } sw59; member