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Searched refs:tRRD (Results 1 – 10 of 10) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/
H A Demif.c31 .tRRD = 10,
55 .tRRD = 10,
84 .tRRD = 2,
H A Dsdram_elpida.c198 .tRRD = 10,
221 .tRRD = 10,
244 .tRRD = 10,
266 .tRRD = 2,
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Demif.c32 .tRRD = 10,
61 .tRRD = 2,
H A Dsdram.c616 .tRRD = 10,
638 .tRRD = 2,
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c133 struct dram_sun9i_timing tRRD; member
393 const u32 tRRD = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps)); in mctl_channel_init() local
552 (MCTL_DIV2(tRRD) << 8) | (MCTL_DIV2(tRP) << 0), in mctl_channel_init()
644 writel((tRC << 26) | (tRRD << 22) | (tRAS << 16) | in mctl_channel_init()
903 .tRRD = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Demif.h1101 u8 tRRD; member
1130 u32 tRRD; member
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg64 # bit27-24: 3, 4 cycle tRRD
H A Dkwbimage-lsxhl.cfg64 # bit27-24: 2, 3 cycle tRRD
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg61 # bit27-24: 2, 3 cycle tRRD
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Demif-common.c608 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; in get_sdram_tim_1_reg()