1*983e3700STom Rini /*
2*983e3700STom Rini * EMIF programming
3*983e3700STom Rini *
4*983e3700STom Rini * (C) Copyright 2010
5*983e3700STom Rini * Texas Instruments, <www.ti.com>
6*983e3700STom Rini *
7*983e3700STom Rini * Aneesh V <aneesh@ti.com> for OMAP4
8*983e3700STom Rini *
9*983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+
10*983e3700STom Rini */
11*983e3700STom Rini
12*983e3700STom Rini #include <common.h>
13*983e3700STom Rini #include <asm/emif.h>
14*983e3700STom Rini #include <asm/arch/sys_proto.h>
15*983e3700STom Rini #include <asm/utils.h>
16*983e3700STom Rini
17*983e3700STom Rini #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
18*983e3700STom Rini #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
19*983e3700STom Rini static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
20*983e3700STom Rini static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
21*983e3700STom Rini #endif
22*983e3700STom Rini
23*983e3700STom Rini #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
24*983e3700STom Rini /* Base AC Timing values specified by JESD209-2 for 532MHz operation */
25*983e3700STom Rini static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
26*983e3700STom Rini .max_freq = 532000000,
27*983e3700STom Rini .RL = 8,
28*983e3700STom Rini .tRPab = 21,
29*983e3700STom Rini .tRCD = 18,
30*983e3700STom Rini .tWR = 15,
31*983e3700STom Rini .tRASmin = 42,
32*983e3700STom Rini .tRRD = 10,
33*983e3700STom Rini .tWTRx2 = 15,
34*983e3700STom Rini .tXSR = 140,
35*983e3700STom Rini .tXPx2 = 15,
36*983e3700STom Rini .tRFCab = 130,
37*983e3700STom Rini .tRTPx2 = 15,
38*983e3700STom Rini .tCKE = 3,
39*983e3700STom Rini .tCKESR = 15,
40*983e3700STom Rini .tZQCS = 90,
41*983e3700STom Rini .tZQCL = 360,
42*983e3700STom Rini .tZQINIT = 1000,
43*983e3700STom Rini .tDQSCKMAXx2 = 11,
44*983e3700STom Rini .tRASmax = 70,
45*983e3700STom Rini .tFAW = 50
46*983e3700STom Rini };
47*983e3700STom Rini
48*983e3700STom Rini /*
49*983e3700STom Rini * Min tCK values specified by JESD209-2
50*983e3700STom Rini * Min tCK specifies the minimum duration of some AC timing parameters in terms
51*983e3700STom Rini * of the number of cycles. If the calculated number of cycles based on the
52*983e3700STom Rini * absolute time value is less than the min tCK value, min tCK value should
53*983e3700STom Rini * be used instead. This typically happens at low frequencies.
54*983e3700STom Rini */
55*983e3700STom Rini static const struct lpddr2_min_tck min_tck_jedec = {
56*983e3700STom Rini .tRL = 3,
57*983e3700STom Rini .tRP_AB = 3,
58*983e3700STom Rini .tRCD = 3,
59*983e3700STom Rini .tWR = 3,
60*983e3700STom Rini .tRAS_MIN = 3,
61*983e3700STom Rini .tRRD = 2,
62*983e3700STom Rini .tWTR = 2,
63*983e3700STom Rini .tXP = 2,
64*983e3700STom Rini .tRTP = 2,
65*983e3700STom Rini .tCKE = 3,
66*983e3700STom Rini .tCKESR = 3,
67*983e3700STom Rini .tFAW = 8
68*983e3700STom Rini };
69*983e3700STom Rini
70*983e3700STom Rini static const struct lpddr2_ac_timings const*
71*983e3700STom Rini jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
72*983e3700STom Rini &timings_jedec_532_mhz
73*983e3700STom Rini };
74*983e3700STom Rini
75*983e3700STom Rini static const struct lpddr2_device_timings jedec_default_timings = {
76*983e3700STom Rini .ac_timings = jedec_ac_timings,
77*983e3700STom Rini .min_tck = &min_tck_jedec
78*983e3700STom Rini };
79*983e3700STom Rini
emif_get_device_timings(u32 emif_nr,const struct lpddr2_device_timings ** cs0_device_timings,const struct lpddr2_device_timings ** cs1_device_timings)80*983e3700STom Rini void emif_get_device_timings(u32 emif_nr,
81*983e3700STom Rini const struct lpddr2_device_timings **cs0_device_timings,
82*983e3700STom Rini const struct lpddr2_device_timings **cs1_device_timings)
83*983e3700STom Rini {
84*983e3700STom Rini /* Assume Identical devices on EMIF1 & EMIF2 */
85*983e3700STom Rini *cs0_device_timings = &jedec_default_timings;
86*983e3700STom Rini *cs1_device_timings = NULL;
87*983e3700STom Rini }
88*983e3700STom Rini #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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