1*983e3700STom Rini /*
2*983e3700STom Rini * EMIF programming
3*983e3700STom Rini *
4*983e3700STom Rini * (C) Copyright 2010
5*983e3700STom Rini * Texas Instruments, <www.ti.com>
6*983e3700STom Rini *
7*983e3700STom Rini * Aneesh V <aneesh@ti.com>
8*983e3700STom Rini *
9*983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+
10*983e3700STom Rini */
11*983e3700STom Rini
12*983e3700STom Rini #include <common.h>
13*983e3700STom Rini #include <asm/emif.h>
14*983e3700STom Rini #include <asm/arch/sys_proto.h>
15*983e3700STom Rini #include <asm/utils.h>
16*983e3700STom Rini
17*983e3700STom Rini #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
18*983e3700STom Rini u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
19*983e3700STom Rini u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
20*983e3700STom Rini #endif
21*983e3700STom Rini
22*983e3700STom Rini #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
23*983e3700STom Rini /* Base AC Timing values specified by JESD209-2 for 400MHz operation */
24*983e3700STom Rini static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
25*983e3700STom Rini .max_freq = 400000000,
26*983e3700STom Rini .RL = 6,
27*983e3700STom Rini .tRPab = 21,
28*983e3700STom Rini .tRCD = 18,
29*983e3700STom Rini .tWR = 15,
30*983e3700STom Rini .tRASmin = 42,
31*983e3700STom Rini .tRRD = 10,
32*983e3700STom Rini .tWTRx2 = 15,
33*983e3700STom Rini .tXSR = 140,
34*983e3700STom Rini .tXPx2 = 15,
35*983e3700STom Rini .tRFCab = 130,
36*983e3700STom Rini .tRTPx2 = 15,
37*983e3700STom Rini .tCKE = 3,
38*983e3700STom Rini .tCKESR = 15,
39*983e3700STom Rini .tZQCS = 90,
40*983e3700STom Rini .tZQCL = 360,
41*983e3700STom Rini .tZQINIT = 1000,
42*983e3700STom Rini .tDQSCKMAXx2 = 11,
43*983e3700STom Rini .tRASmax = 70,
44*983e3700STom Rini .tFAW = 50
45*983e3700STom Rini };
46*983e3700STom Rini
47*983e3700STom Rini /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
48*983e3700STom Rini static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
49*983e3700STom Rini .max_freq = 200000000,
50*983e3700STom Rini .RL = 3,
51*983e3700STom Rini .tRPab = 21,
52*983e3700STom Rini .tRCD = 18,
53*983e3700STom Rini .tWR = 15,
54*983e3700STom Rini .tRASmin = 42,
55*983e3700STom Rini .tRRD = 10,
56*983e3700STom Rini .tWTRx2 = 20,
57*983e3700STom Rini .tXSR = 140,
58*983e3700STom Rini .tXPx2 = 15,
59*983e3700STom Rini .tRFCab = 130,
60*983e3700STom Rini .tRTPx2 = 15,
61*983e3700STom Rini .tCKE = 3,
62*983e3700STom Rini .tCKESR = 15,
63*983e3700STom Rini .tZQCS = 90,
64*983e3700STom Rini .tZQCL = 360,
65*983e3700STom Rini .tZQINIT = 1000,
66*983e3700STom Rini .tDQSCKMAXx2 = 11,
67*983e3700STom Rini .tRASmax = 70,
68*983e3700STom Rini .tFAW = 50
69*983e3700STom Rini };
70*983e3700STom Rini
71*983e3700STom Rini /*
72*983e3700STom Rini * Min tCK values specified by JESD209-2
73*983e3700STom Rini * Min tCK specifies the minimum duration of some AC timing parameters in terms
74*983e3700STom Rini * of the number of cycles. If the calculated number of cycles based on the
75*983e3700STom Rini * absolute time value is less than the min tCK value, min tCK value should
76*983e3700STom Rini * be used instead. This typically happens at low frequencies.
77*983e3700STom Rini */
78*983e3700STom Rini static const struct lpddr2_min_tck min_tck_jedec = {
79*983e3700STom Rini .tRL = 3,
80*983e3700STom Rini .tRP_AB = 3,
81*983e3700STom Rini .tRCD = 3,
82*983e3700STom Rini .tWR = 3,
83*983e3700STom Rini .tRAS_MIN = 3,
84*983e3700STom Rini .tRRD = 2,
85*983e3700STom Rini .tWTR = 2,
86*983e3700STom Rini .tXP = 2,
87*983e3700STom Rini .tRTP = 2,
88*983e3700STom Rini .tCKE = 3,
89*983e3700STom Rini .tCKESR = 3,
90*983e3700STom Rini .tFAW = 8
91*983e3700STom Rini };
92*983e3700STom Rini
93*983e3700STom Rini static const struct lpddr2_ac_timings const*
94*983e3700STom Rini jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
95*983e3700STom Rini &timings_jedec_200_mhz,
96*983e3700STom Rini &timings_jedec_400_mhz
97*983e3700STom Rini };
98*983e3700STom Rini
99*983e3700STom Rini const struct lpddr2_device_timings jedec_default_timings = {
100*983e3700STom Rini .ac_timings = jedec_ac_timings,
101*983e3700STom Rini .min_tck = &min_tck_jedec
102*983e3700STom Rini };
103*983e3700STom Rini
emif_get_device_timings(u32 emif_nr,const struct lpddr2_device_timings ** cs0_device_timings,const struct lpddr2_device_timings ** cs1_device_timings)104*983e3700STom Rini void emif_get_device_timings(u32 emif_nr,
105*983e3700STom Rini const struct lpddr2_device_timings **cs0_device_timings,
106*983e3700STom Rini const struct lpddr2_device_timings **cs1_device_timings)
107*983e3700STom Rini {
108*983e3700STom Rini /* Assume Identical devices on EMIF1 & EMIF2 */
109*983e3700STom Rini *cs0_device_timings = &jedec_default_timings;
110*983e3700STom Rini *cs1_device_timings = &jedec_default_timings;
111*983e3700STom Rini }
112*983e3700STom Rini #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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