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Searched refs:im (Results 1 – 25 of 28) sorted by relevance

12

/rk3399_rockchip-uboot/board/freescale/mpc8315erdb/
H A Dsdram.c44 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
48 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
49 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); in fixed_sdram()
50 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in fixed_sdram()
58 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; in fixed_sdram()
59 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
62 im->ddr.cs_config[1] = 0; in fixed_sdram()
64 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
65 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
66 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc8313erdb/
H A Dsdram.c48 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
51 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
52 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); in fixed_sdram()
53 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in fixed_sdram()
64 im->ddr.csbnds[0].csbnds = in fixed_sdram()
68 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
71 im->ddr.cs_config[1] = 0; in fixed_sdram()
73 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; in fixed_sdram()
74 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
75 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
[all …]
H A Dmpc8313erdb.c27 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in board_early_init_f() local
29 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) in board_early_init_f()
/rk3399_rockchip-uboot/board/freescale/mpc8308rdb/
H A Dsdram.c32 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
36 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
38 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
39 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
41 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
42 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
45 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
47 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
48 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/mpc8308_p1m/
H A Dsdram.c28 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
32 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
34 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
35 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
37 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
38 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
41 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
43 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
44 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
45 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/gdsys/mpc8308/
H A Dsdram.c33 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
37 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
39 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
40 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
42 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
43 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
46 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
48 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc8349emds/
H A Dmpc8349emds.c53 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
56 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
60 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
90 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
95 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
96 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); in fixed_sdram()
102 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; in fixed_sdram()
103 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; in fixed_sdram()
104 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
105 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc832xemds/
H A Dmpc832xemds.c95 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in dram_init() local
98 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
102 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
117 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in fixed_sdram() local
129 im->sysconf.ddrlaw[0].ar = in fixed_sdram()
134 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; in fixed_sdram()
135 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
136 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
137 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
138 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/drivers/gpio/
H A Dmpc83xx_gpio.c54 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_direction_input() local
66 clrbits_be32(&im->gpio[ctrlr].dir, line_mask); in gpio_direction_input()
74 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_direction_output() local
94 setbits_be32(&im->gpio[ctrlr].dir, line_mask); in gpio_direction_output()
102 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_get_value() local
115 return (in_be32(&im->gpio[ctrlr].dat) & line_mask) != 0; in gpio_get_value()
121 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_set_value() local
144 out_be32(&im->gpio[ctrlr].dat, gpio_output_value[ctrlr]); in gpio_set_value()
152 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in mpc83xx_gpio_init_f() local
155 out_be32(&im->gpio[0].dir, CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION); in mpc83xx_gpio_init_f()
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc8349itx/
H A Dmpc8349itx.c31 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in fixed_sdram() local
36 im->sysconf.ddrlaw[0].ar = in fixed_sdram()
38 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
43 im->ddr.csbnds[0].csbnds = in fixed_sdram()
47 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
50 im->ddr.cs_config[1] = 0; in fixed_sdram()
51 im->ddr.cs_config[2] = 0; in fixed_sdram()
52 im->ddr.cs_config[3] = 0; in fixed_sdram()
54 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); in fixed_sdram()
55 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/ve8313/
H A Dve8313.c38 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
41 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
43 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); in fixed_sdram()
44 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
55 out_be32(&im->ddr.csbnds[0].csbnds, in fixed_sdram()
59 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
62 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
64 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); in fixed_sdram()
65 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
66 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/ids/ids8313/
H A Dids8313.c54 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
60 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
62 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); in fixed_sdram()
63 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
72 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
73 out_be32(&im->ddr.cs_config[0], config); in fixed_sdram()
76 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
77 out_be32(&im->ddr.cs_config[2], 0); in fixed_sdram()
78 out_be32(&im->ddr.cs_config[3], 0); in fixed_sdram()
80 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dcpu_init.c49 void cpu_init_f (volatile immap_t * im) in cpu_init_f() argument
212 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); in cpu_init_f()
214 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); in cpu_init_f()
216 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); in cpu_init_f()
219 gd->arch.reset_status = __raw_readl(&im->reset.rsr); in cpu_init_f()
220 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
223 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); in cpu_init_f()
224 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr); in cpu_init_f()
230 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr); in cpu_init_f()
235 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val); in cpu_init_f()
[all …]
H A Dspl_minimal.c19 void cpu_init_f (volatile immap_t * im) in cpu_init_f() argument
30 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | in cpu_init_f()
36 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | in cpu_init_f()
42 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | in cpu_init_f()
47 im->sysconf.spcr |= SPCR_TBEN; in cpu_init_f()
51 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; in cpu_init_f()
55 im->sysconf.obir = CONFIG_SYS_OBIR; in cpu_init_f()
73 im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; in cpu_init_f()
74 im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; in cpu_init_f()
H A Dspeed.c77 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in get_clocks() local
133 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in get_clocks()
136 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); in get_clocks()
138 if (im->reset.rcwh & HRCWH_PCI_HOST) { in get_clocks()
152 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; in get_clocks()
155 sccr = im->clk.sccr; in get_clocks()
392 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); in get_clocks()
393 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; in get_clocks()
406 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); in get_clocks()
407 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT; in get_clocks()
[all …]
H A Dqe_io.c23 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in qe_config_iopin() local
24 volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; in qe_config_iopin()
/rk3399_rockchip-uboot/board/freescale/mpc837xerdb/
H A Dmpc837xerdb.c67 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in dram_init() local
70 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
95 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in fixed_sdram() local
99 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
100 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); in fixed_sdram()
102 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in fixed_sdram()
105 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
108 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
109 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
112 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/sbc8349/
H A Dsbc8349.c42 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
45 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
49 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
78 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
83 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
84 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); in fixed_sdram()
93 im->ddr.csbnds[2].csbnds = in fixed_sdram()
97 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; in fixed_sdram()
100 im->ddr.cs_config[0] = 0; in fixed_sdram()
101 im->ddr.cs_config[1] = 0; in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc8323erdb/
H A Dmpc8323erdb.c75 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in dram_init() local
78 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
82 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
97 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in fixed_sdram() local
109 im->sysconf.ddrlaw[0].ar = in fixed_sdram()
111 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; in fixed_sdram()
112 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
113 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
114 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
115 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc837xemds/
H A Dmpc837xemds.c66 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; in board_mmc_init() local
76 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); in board_mmc_init()
77 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI, in board_mmc_init()
89 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; in board_eth_init() local
90 u32 rcwh = in_be32(&im->reset.rcwh); in board_eth_init()
188 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; in ft_tsec_fixup() local
189 u32 rcwh = in_be32(&im->reset.rcwh); in ft_tsec_fixup()
223 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in dram_init() local
226 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
252 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in fixed_sdram() local
[all …]
/rk3399_rockchip-uboot/board/keymile/km83xx/
H A Dkm83xx.c292 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
297 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); in fixed_sdram()
298 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); in fixed_sdram()
299 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
300 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
301 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
302 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
303 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
304 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
305 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/rk3399_rockchip-uboot/board/tqc/tqm834x/
H A Dtqm834x.c51 static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; variable
59 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in board_early_init_r()
76 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; in dram_init()
77 im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); in dram_init()
94 im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | in dram_init()
323 im->ddr.csbnds[cs].csbnds = 0x00000000; in set_cs_bounds()
325 im->ddr.csbnds[cs].csbnds = in set_cs_bounds()
340 im->ddr.cs_config[cs] = config; in set_cs_config()
349 im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | in set_ddr_config()
354 im->ddr.timing_cfg_1 = in set_ddr_config()
[all …]
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_mpc8xx.c64 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; in smc_setbrg() local
65 cpm8xx_t __iomem *cp = &(im->im_cpm); in smc_setbrg()
80 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; in smc_init() local
83 cpm8xx_t __iomem *cp = &(im->im_cpm); in smc_init()
97 out_be32(&im->im_siu_conf.sc_sdcr, 1); in smc_init()
100 out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR); in smc_init()
103 out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR); in smc_init()
172 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; in smc_putc() local
173 cpm8xx_t __iomem *cpmp = &(im->im_cpm); in smc_putc()
198 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; in smc_getc() local
[all …]
/rk3399_rockchip-uboot/include/
H A Dioports.h27 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) argument
29 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) argument
/rk3399_rockchip-uboot/board/esd/vme8349/
H A Dvme8349.c35 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
38 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
42 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
95 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in misc_init_r() local
97 clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0); in misc_init_r()

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