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Searched refs:ddr_clk (Results 1 – 10 of 10) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk_mipi.c207 u64 ddr_clk = priv->phy_clk; in rk_mipi_phy_enable() local
234 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; in rk_mipi_phy_enable()
245 if (ddr_clk / (MHz) >= freq_rang[i][0]) in rk_mipi_phy_enable()
275 if ((ddr_clk * i % refclk < remain) && in rk_mipi_phy_enable()
276 (ddr_clk * i / refclk) < max_fbdiv) { in rk_mipi_phy_enable()
278 remain = ddr_clk * i % refclk; in rk_mipi_phy_enable()
281 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
282 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
283 priv->phy_clk = ddr_clk; in rk_mipi_phy_enable()
286 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dclocks-common.c270 u32 ddr_clk, sys_clk_khz, omap_rev, divider; in omap_ddr_clk() local
281 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / in omap_ddr_clk()
298 ddr_clk = ddr_clk / divider / core_dpll_params->m2; in omap_ddr_clk()
299 ddr_clk *= 1000; /* convert to Hz */ in omap_ddr_clk()
300 debug("ddr_clk %d\n ", ddr_clk); in omap_ddr_clk()
302 return ddr_clk; in omap_ddr_clk()
/rk3399_rockchip-uboot/arch/arm/mach-aspeed/ast2500/
H A Dsdram_ast2500.c69 struct clk ddr_clk; member
335 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in ast2500_sdrammc_probe()
348 clk_set_rate(&priv->ddr_clk, priv->clock_rate); in ast2500_sdrammc_probe()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk322x.c35 struct clk ddr_clk; member
690 ret = clk_set_rate(&dram->ddr_clk, in sdram_init()
800 priv->ddr_clk.id = CLK_DDR; in rk322x_dmc_probe()
801 ret = clk_request(dev_clk, &priv->ddr_clk); in rk322x_dmc_probe()
H A Ddmc-rk3368.c27 struct clk ddr_clk; member
810 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); in setup_sdram()
946 priv->ddr_clk.id = CLK_DDR; in rk3368_dmc_probe()
947 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3368_dmc_probe()
H A Dsdram_rk3188.c39 struct clk ddr_clk; member
725 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
909 priv->ddr_clk.id = CLK_DDR; in rk3188_dmc_probe()
910 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3188_dmc_probe()
H A Dsdram_rk3288.c41 struct clk ddr_clk; member
800 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
1074 priv->ddr_clk.id = CLK_DDR; in rk3288_dmc_probe()
1075 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3288_dmc_probe()
H A Dsdram_rk3399.c39 struct clk ddr_clk; member
2855 ret_clk = clk_set_rate(&dram->ddr_clk, hz); in dram_set_rate()
3139 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); in rk3399_dmc_init()
3141 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in rk3399_dmc_init()
3147 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); in rk3399_dmc_init()
H A Dsdram_rk3328.c28 struct clk ddr_clk; member
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c39 struct clk ddr_clk; member
705 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
891 priv->ddr_clk.id = CLK_DDR; in rk3066_dmc_probe()
893 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3066_dmc_probe()