| /rk3399_ARM-atf/drivers/nxp/console/ |
| H A D | linflex_console.S | 66 ldr w4, [x0, LINFLEX_UARTCR]
67 mov w5, w4
73 and w4, w4, #UARTCR_ROSE
74 cmp w4, #0x0
75 csel w4, w5, w6, ne
120 mov w4, #(LINCR1_INIT)
121 str w4, [x0, LINFLEX_LINCR1]
122 mov w4, #(LINCR1_MME | LINCR1_INIT)
123 str w4, [x0, LINFLEX_LINCR1]
127 ldr w4, [x0, LINFLEX_LINSR]
[all …]
|
| /rk3399_ARM-atf/plat/nxp/soc-lx2160a/aarch64/ |
| H A D | lx2160a.S | 360 ldr w4, [x6, #GICR_CTLR_OFFSET]
361 tst w4, #GICR_CTLR_RWP
373 ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
374 bic w4, w4, #GICR_IGROUPR0_SGI15
375 str w4, [x5, #GICR_IGROUPR0_OFFSET]
383 ldr w4, [x5, #GICR_IPRIORITYR3_OFFSET]
384 bic w4, w4, #GICR_IPRIORITYR3_SGI15_MASK
385 str w4, [x5, #GICR_IPRIORITYR3_OFFSET]
394 ldr w4, [x6, #GICR_CTLR_OFFSET]
395 tst w4, #GICR_CTLR_RWP
[all …]
|
| /rk3399_ARM-atf/drivers/st/uart/aarch64/ |
| H A D | stm32_console.S | 64 mov w4, #USART_CR1_UE
65 bic w3, w3, w4
68 mov w4, #(USART_CR1_TE)
69 orr w4, w4, #(USART_CR1_FIFOEN)
70 orr w3, w3, w4
73 mov w4, #USART_CR2_STOP
74 bic w3, w3, w4
98 mov w4, #USART_CR1_UE
99 orr w3, w3, w4
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1088a/aarch64/ |
| H A D | ls1088a.S | 370 ldr w4, [x6, #GICR_CTLR_OFFSET]
371 tst w4, #GICR_CTLR_RWP
383 ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
384 bic w4, w4, #GICR_IGROUPR0_SGI15
385 str w4, [x5, #GICR_IGROUPR0_OFFSET]
393 ldr w4, [x5, #GICR_IPRIORITYR3_OFFSET]
394 bic w4, w4, #GICR_IPRIORITYR3_SGI15_MASK
395 str w4, [x5, #GICR_IPRIORITYR3_OFFSET]
404 ldr w4, [x6, #GICR_CTLR_OFFSET]
405 tst w4, #GICR_CTLR_RWP
[all …]
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1028a/aarch64/ |
| H A D | ls1028a.S | 327 ldr w4, [x6, #GICR_CTLR_OFFSET]
328 tst w4, #GICR_CTLR_RWP
340 ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
341 bic w4, w4, #GICR_IGROUPR0_SGI15
342 str w4, [x5, #GICR_IGROUPR0_OFFSET]
350 ldr w4, [x5, #GICR_IPRIORITYR3_OFFSET]
351 bic w4, w4, #GICR_IPRIORITYR3_SGI15_MASK
352 str w4, [x5, #GICR_IPRIORITYR3_OFFSET]
361 ldr w4, [x6, #GICR_CTLR_OFFSET]
362 tst w4, #GICR_CTLR_RWP
[all …]
|
| /rk3399_ARM-atf/drivers/marvell/uart/ |
| H A D | a3700_console.S | 51 mov w4, #30 /* max time out 30 * 100 us */
67 sub w4, w4, #1
68 cmp w4, #0
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1043a/aarch64/ |
| H A D | ls1043a.S | 1492 rev w4, w3
1493 orr w4, w4, w2
1494 rev w3, w4
1497 rev w4, w3
1498 str w4, [x7, #RCPM2_IPSTPCR4_OFFSET] /* quiesce ddr clocks - end */
1514 rev w4, w5
1515 str w4, [x7, #RCPM2_IPSTPCR4_OFFSET] /* re-enable ddr clks interface */
1519 str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* disable ddr cntrlr clk in devdisr5 */
1524 rev w4, w5
1525 str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* re-enable ddr in devdisr5 */
[all …]
|
| /rk3399_ARM-atf/plat/amd/versal2/aarch64/ |
| H A D | helpers.S | 52 mov w4, #PLAT_INVALID_CPU_CORE
53 cmp w3, w4
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1046a/aarch64/ |
| H A D | ls1046a.S | 360 ldr w4, [x5, #SYS_COUNTER_CNTCR_OFFSET]
361 mov w2, w4
367 orr w4, w4, #CNTCR_EN_MASK
368 str w4, [x5, #SYS_COUNTER_CNTCR_OFFSET]
673 rbit w1, w4
731 rbit w1, w4
791 rbit w1, w4
834 rbit w1, w4
|
| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | crash_reporting.S | 96 ldrb w4, [x6]
98 cbz w4, exit_size_print
250 ldrb w4, [x6]
252 cbz w4, print_x30
|
| /rk3399_ARM-atf/plat/nvidia/tegra/include/ |
| H A D | plat_macros.S | 55 ldr w4, [x7], #4
|
| /rk3399_ARM-atf/drivers/arm/pl011/aarch64/ |
| H A D | pl011_console.S | 48 mov w4, #PL011_UARTCR_UARTEN
49 bic w3, w3, w4
|
| /rk3399_ARM-atf/lib/aarch64/ |
| H A D | cache_helpers.S | 200 clz w5, w4 // bit position of way size increment
201 lsl w9, w4, w5 // w9 = aligned max way number
|
| /rk3399_ARM-atf/plat/imx/imx8ulp/xrdc/ |
| H A D | xrdc_core.c | 111 static int xrdc_config_mrc_w3_w4(uint32_t mrc_con, uint32_t region, uint32_t w3, uint32_t w4) in xrdc_config_mrc_w3_w4() argument
117 mmio_write_32(w4_addr, w4); in xrdc_config_mrc_w3_w4()
|
| /rk3399_ARM-atf/plat/intel/soc/common/aarch64/ |
| H A D | plat_helpers.S | 165 ldrb w4, [x4, #3]
|