1c97857dbSAmit Nagal/* 2c97857dbSAmit Nagal * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3c97857dbSAmit Nagal * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4*d2244f32SPrasad Kummari * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5c97857dbSAmit Nagal * 6c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 7c97857dbSAmit Nagal */ 8c97857dbSAmit Nagal 9c97857dbSAmit Nagal#include <arch.h> 10c97857dbSAmit Nagal#include <asm_macros.S> 11c97857dbSAmit Nagal#include <drivers/arm/gicv3.h> 12c97857dbSAmit Nagal 13c97857dbSAmit Nagal#include <platform_def.h> 14c97857dbSAmit Nagal 15c97857dbSAmit Nagal .globl plat_secondary_cold_boot_setup 16c97857dbSAmit Nagal .globl plat_is_my_cpu_primary 17c97857dbSAmit Nagal .globl platform_mem_init 18c97857dbSAmit Nagal .globl plat_my_core_pos 19*d2244f32SPrasad Kummari .globl plat_core_pos_by_mpidr 20*d2244f32SPrasad Kummari 21c97857dbSAmit Nagal 22c97857dbSAmit Nagal /* ----------------------------------------------------- 23c97857dbSAmit Nagal * void plat_secondary_cold_boot_setup (void); 24c97857dbSAmit Nagal * 25c97857dbSAmit Nagal * This function performs any platform specific actions 26c97857dbSAmit Nagal * needed for a secondary cpu after a cold reset e.g 27c97857dbSAmit Nagal * mark the cpu's presence, mechanism to place it in a 28c97857dbSAmit Nagal * holding pen etc. 29c97857dbSAmit Nagal * TODO: Should we read the PSYS register to make sure 30c97857dbSAmit Nagal * that the request has gone through. 31c97857dbSAmit Nagal * ----------------------------------------------------- 32c97857dbSAmit Nagal */ 33c97857dbSAmit Nagalfunc plat_secondary_cold_boot_setup 34c97857dbSAmit Nagal mrs x0, mpidr_el1 35c97857dbSAmit Nagal 36c97857dbSAmit Nagal /* 37c97857dbSAmit Nagal * There is no sane reason to come out of this wfi. This 38c97857dbSAmit Nagal * cpu will be powered on and reset by the cpu_on pm api 39c97857dbSAmit Nagal */ 40c97857dbSAmit Nagal dsb sy 41c97857dbSAmit Nagal bl plat_panic_handler 42c97857dbSAmit Nagalendfunc plat_secondary_cold_boot_setup 43c97857dbSAmit Nagal 44c97857dbSAmit Nagalfunc plat_is_my_cpu_primary 45c97857dbSAmit Nagal mov x9, x30 46c97857dbSAmit Nagal bl plat_my_core_pos 47c97857dbSAmit Nagal cmp x0, #PRIMARY_CPU 48c97857dbSAmit Nagal cset x0, eq 49c97857dbSAmit Nagal ret x9 50c97857dbSAmit Nagalendfunc plat_is_my_cpu_primary 51c97857dbSAmit Nagal 52c97857dbSAmit Nagal /* ----------------------------------------------------- 53c97857dbSAmit Nagal * unsigned int plat_my_core_pos(void) 54c97857dbSAmit Nagal * This function uses the plat_core_pos_by_mpidr() 55c97857dbSAmit Nagal * definition to get the index of the calling CPU. 56c97857dbSAmit Nagal * ----------------------------------------------------- 57c97857dbSAmit Nagal */ 58c97857dbSAmit Nagalfunc plat_my_core_pos 59c97857dbSAmit Nagal mrs x0, mpidr_el1 60c97857dbSAmit Nagal b plat_core_pos_by_mpidr 61c97857dbSAmit Nagalendfunc plat_my_core_pos 62c97857dbSAmit Nagal 63*d2244f32SPrasad Kummari /*---------------------------------------------------------------------- 64*d2244f32SPrasad Kummari * unsigned int plat_core_pos_by_mpidr(u_register_t mpid) 65*d2244f32SPrasad Kummari * 66*d2244f32SPrasad Kummari * Function to calculate the core position 67*d2244f32SPrasad Kummari * 68*d2244f32SPrasad Kummari * clobbers: x0 - x3 69*d2244f32SPrasad Kummari * --------------------------------------------------------------------- 70*d2244f32SPrasad Kummari */ 71*d2244f32SPrasad Kummarifunc plat_core_pos_by_mpidr 72*d2244f32SPrasad Kummari 73*d2244f32SPrasad Kummari /* Extract individual affinity fields from MPIDR */ 74*d2244f32SPrasad Kummari ubfx x1, x0, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 75*d2244f32SPrasad Kummari ubfx x2, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 76*d2244f32SPrasad Kummari 77*d2244f32SPrasad Kummari /* check if cpu_id valid */ 78*d2244f32SPrasad Kummari cmp x2, #PLATFORM_CORE_COUNT_PER_CLUSTER 79*d2244f32SPrasad Kummari b.hi error_invalid_core 80*d2244f32SPrasad Kummari 81*d2244f32SPrasad Kummari /* check if cluster valid */ 82*d2244f32SPrasad Kummari cmp x1, #PLATFORM_CLUSTER_COUNT 83*d2244f32SPrasad Kummari b.hi error_invalid_cluster 84*d2244f32SPrasad Kummari 85*d2244f32SPrasad Kummari /* Compute linear position */ 86*d2244f32SPrasad Kummari mov x3, #PLATFORM_CORE_COUNT_PER_CLUSTER 87*d2244f32SPrasad Kummari madd x0, x1, x3, x2 88*d2244f32SPrasad Kummari ret 89*d2244f32SPrasad Kummarierror_invalid_cluster: 90*d2244f32SPrasad Kummari mov x0, #E_INVALID_CLUSTER_COUNT 91*d2244f32SPrasad Kummari ret 92*d2244f32SPrasad Kummarierror_invalid_core: 93*d2244f32SPrasad Kummari mov x0, #E_INVALID_CORE_COUNT 94*d2244f32SPrasad Kummari ret 95*d2244f32SPrasad Kummariendfunc plat_core_pos_by_mpidr 96*d2244f32SPrasad Kummari 97c97857dbSAmit Nagal /* --------------------------------------------------------------------- 98c97857dbSAmit Nagal * We don't need to carry out any memory initialization on platform 99c97857dbSAmit Nagal * The Secure RAM is accessible straight away. 100c97857dbSAmit Nagal * --------------------------------------------------------------------- 101c97857dbSAmit Nagal */ 102c97857dbSAmit Nagalfunc platform_mem_init 103c97857dbSAmit Nagal ret 104c97857dbSAmit Nagalendfunc platform_mem_init 105