| /rk3399_ARM-atf/plat/arm/board/morello/fdts/ |
| H A D | morello_nt_fw_config.dts | 15 * the BL2 stage of boot. 30 * the BL2 stage of boot.
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| /rk3399_ARM-atf/docs/process/ |
| H A D | platform-ports-policy.rst | 40 can be a 1-stage or 2-stage process (up to the maintainers). 42 - *2-stage*: The source code can be kept in the repository for a cooling off 46 - *1-stage*: The source code can be deleted straight away. In this case, both
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| /rk3399_ARM-atf/plat/mediatek/drivers/ufs/ |
| H A D | ufs_stub.c | 12 void ufs_ref_clk_status(uint32_t on, enum ufs_notify_change_status stage) {} in ufs_ref_clk_status() argument
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| /rk3399_ARM-atf/plat/arm/board/n1sdp/fdts/ |
| H A D | n1sdp_nt_fw_config.dts | 15 * the BL2 stage of boot.
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/fdts/ |
| H A D | rdv3_nt_fw_config.dts | 15 * correct values during the BL2 stage of boot.
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| /rk3399_ARM-atf/docs/plat/marvell/armada/misc/ |
| H A D | mvebu-ccu.rst | 4 CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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| H A D | mvebu-io-win.rst | 4 IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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| H A D | mvebu-iob.rst | 4 IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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| /rk3399_ARM-atf/docs/plat/ |
| H A D | npcm845x.rst | 11 Every stage is measured and validated by the bootblock.
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| H A D | s32g274a.rst | 26 upcoming S32G2 contributions. The execution will hang after the BL31 stage 46 stage. This means that important drivers like DDR and storage are not yet
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| H A D | socionext-uniphier.rst | 13 To solve this issue, Socionext provides a first stage loader called
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| H A D | rpi4.rst | 60 run after the SoC gets its power. The on-chip Boot ROM loads the next stage
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/fdts/ |
| H A D | rdn2_nt_fw_config.dts | 15 * correct values during the BL2 stage of boot.
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| /rk3399_ARM-atf/plat/mediatek/include/ |
| H A D | mtk_bl31_interface.h | 48 void ufs_ref_clk_status(uint32_t on, enum ufs_notify_change_status stage);
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| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | image-terminology.rst | 63 This is the 2nd stage AP firmware. It is currently also known as the "Trusted 130 This is the 2nd stage SCP firmware. It is currently also known as the "SCP 135 this has always been the 2nd stage firmware. The previous name is too 174 This is the 2nd stage AP normal world firmware updater. Its primary purpose is
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| H A D | initial-build.rst | 89 the objects and binaries for each boot loader stage in separate
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| /rk3399_ARM-atf/docs/plat/arm/tc/ |
| H A D | index.rst | 30 stages including BL31 runtime stage and hands off executing to
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| /rk3399_ARM-atf/plat/imx/imx8ulp/upower/ |
| H A D | upower_api.h | 708 int upwr_pwm_freq_setup(soc_domain_t domain, uint32_t rail, uint32_t stage,
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| H A D | upower_api.c | 2108 int upwr_pwm_freq_setup(soc_domain_t domain, uint32_t rail, uint32_t stage, uint32_t target_freq, in upwr_pwm_freq_setup() argument 2127 txmsg.args.stage = stage; in upwr_pwm_freq_setup()
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| H A D | upower_defs.h | 444 uint32_t stage : 2; /* DVA stage */ member
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| /rk3399_ARM-atf/docs/threat_model/firmware_threat_model/ |
| H A D | threat_model_firmware_handoff.rst | 52 | DF7 | | Information produced during any stage of the AP boot | 128 | | stage relocates a TL from one location to another |
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| /rk3399_ARM-atf/docs/design/ |
| H A D | firmware-design.rst | 9 to the stage where it hands-off control to firmware running in the normal 52 - Boot Loader stage 1 (BL1) *AP Trusted ROM* 53 - Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54 - Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55 - Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56 - Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 60 - Boot Loader stage 1 (BL1) *AP Trusted ROM* 61 - Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62 - Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63 - Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* [all …]
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| /rk3399_ARM-atf/docs/design_documents/ |
| H A D | drtm_poc.rst | 35 stage of DRTM, the DCE. The D-CRTM measures the DCE, verifies its
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| /rk3399_ARM-atf/docs/plat/arm/automotive_rd/ |
| H A D | rdaspen.rst | 27 The following tasks are executed for each AP BL stage:
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| /rk3399_ARM-atf/docs/components/ |
| H A D | firmware-update.rst | 41 the second stage Bootloader after FWU has been done by ``Client`` and 55 On subsequent reboot, the second stage Bootloader (BL2) performs the 73 The second stage Bootloader (BL2) avoids upgrading the platform NV-counter until
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