1*cf85030eSsahil/* 2*cf85030eSsahil * Copyright (c) 2022, Arm Limited. All rights reserved. 3*cf85030eSsahil * 4*cf85030eSsahil * SPDX-License-Identifier: BSD-3-Clause 5*cf85030eSsahil */ 6*cf85030eSsahil 7*cf85030eSsahil/dts-v1/; 8*cf85030eSsahil/ { 9*cf85030eSsahil /* compatible string */ 10*cf85030eSsahil compatible = "arm,n1sdp"; 11*cf85030eSsahil 12*cf85030eSsahil /* 13*cf85030eSsahil * Place holder for platform-info node with default values. 14*cf85030eSsahil * The values will be set to the correct values during 15*cf85030eSsahil * the BL2 stage of boot. 16*cf85030eSsahil */ 17*cf85030eSsahil platform-info { 18*cf85030eSsahil multichip-mode = <0x0>; 19*cf85030eSsahil secondary-chip-count = <0x0>; 20*cf85030eSsahil local-ddr-size = <0x0>; 21*cf85030eSsahil remote-ddr-size = <0x0>; 22*cf85030eSsahil }; 23*cf85030eSsahil};