| #
978a316b |
| 29-Aug-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(s32g274a): update compilation instructions" into integration
|
| #
2074600e |
| 08-Aug-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
docs(s32g274a): update compilation instructions
Changes to the Poetry memory module have removed
support for the `-f` option, following commit
8daebefe59e ("refactor(memmap)!: change behavioural fla
docs(s32g274a): update compilation instructions
Changes to the Poetry memory module have removed
support for the `-f` option, following commit
8daebefe59e ("refactor(memmap)!: change behavioural flags to commands").
This update replaces `-f` with `footprint` option
to ensure compatibility with the updated memory
module.
Change-Id: I58eb2c5e9ca649c7a00696b0a3b5c8e02fa29c84
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
show more ...
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| #
bccc2275 |
| 27-Sep-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "nxp-s32g274a/err051700" into integration
* changes:
feat(s32g274a): enable workaround for ERR051700
fix(s32g274a): workaround for ERR051700 erratum
|
| #
b47d085a |
| 12-Sep-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
fix(s32g274a): workaround for ERR051700 erratum
ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneo
fix(s32g274a): workaround for ERR051700 erratum
ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.
The workaround is to clear the SRD resets sequentially instead of
simultaneously.
Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| #
4bd1e7bd |
| 08-May-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "add_s32g274ardb2_support" into integration
* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex
Merge changes from topic "add_s32g274ardb2_support" into integration
* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex driver
show more ...
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| #
8b81a39e |
| 30-Jan-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(s32g274a): add S32G274ARDB2 board support
S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, a
feat(s32g274a): add S32G274ARDB2 board support
S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.
The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.
Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
show more ...
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