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Searched refs:resets (Results 1 – 17 of 17) sorted by relevance

/rk3399_ARM-atf/fdts/
H A Dstm32mp251.dtsi9 #include <dt-bindings/reset/stm32mp25-resets.h>
97 resets = <&rcc USART2_R>;
105 resets = <&rcc USART3_R>;
113 resets = <&rcc UART4_R>;
121 resets = <&rcc UART5_R>;
129 resets = <&rcc I2C1_R>;
137 resets = <&rcc I2C2_R>;
145 resets = <&rcc I2C3_R>;
153 resets = <&rcc I2C4_R>;
161 resets = <&rcc I2C5_R>;
[all …]
H A Dstm32mp131.dtsi8 #include <dt-bindings/reset/stm32mp13-resets.h>
86 resets = <&rcc USART3_R>;
95 resets = <&rcc UART4_R>;
104 resets = <&rcc UART5_R>;
113 resets = <&rcc UART7_R>;
122 resets = <&rcc UART8_R>;
131 resets = <&rcc USART6_R>;
140 resets = <&rcc USBO_R>;
156 resets = <&rcc USART1_R>;
165 resets = <&rcc USART2_R>;
[all …]
H A Dstm32mp151.dtsi8 #include <dt-bindings/reset/stm32mp1-resets.h>
94 resets = <&rcc USART2_R>;
103 resets = <&rcc USART3_R>;
112 resets = <&rcc UART4_R>;
122 resets = <&rcc UART5_R>;
133 resets = <&rcc I2C2_R>;
146 resets = <&rcc UART7_R>;
155 resets = <&rcc UART8_R>;
164 resets = <&rcc USART6_R>;
183 resets = <&rcc USBO_R>;
[all …]
H A Dstm32mp13xf.dtsi14 resets = <&rcc SAES_R>;
22 resets = <&rcc PKA_R>;
H A Dstm32mp13xc.dtsi15 resets = <&rcc SAES_R>;
23 resets = <&rcc PKA_R>;
H A Dstm32mp15xc.dtsi14 resets = <&rcc CRYP1_R>;
/rk3399_ARM-atf/drivers/ti/ti_sci/
H A Dti_sci_protocol.h233 uint32_t resets; member
257 uint32_t resets; member
H A Dti_sci.c317 uint32_t *resets, uint8_t *p_state, in ti_sci_device_get_state() argument
326 if (!clcnt && !resets && !p_state && !c_state) in ti_sci_device_get_state()
348 if (resets) in ti_sci_device_get_state()
349 *resets = resp.resets; in ti_sci_device_get_state()
655 req.resets = reset_state; in ti_sci_device_set_resets()
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-5.rst48 here ``PMCR_EL0.DP`` architecturally resets to zero.
/rk3399_ARM-atf/docs/plat/st/
H A Dstm32mpus.rst11 The STM32 MPU resets in the ROM code of the Cortex-A.
/rk3399_ARM-atf/docs/design/
H A Dreset-design.rst5 resets in Trusted Firmware-A (TF-A). It also describes how the platform
144 In this configuration, since the CPU resets to BL31, no parameters are expected
/rk3399_ARM-atf/docs/process/
H A Dsecurity-hardening.rst95 - ``MDCR_EL3.SPME`` resets to ``0``, so by default general events should
H A Dcoding-guidelines.rst303 it may set a flag so the platform resets into a different mode). Also,
/rk3399_ARM-atf/docs/plat/
H A Drz-g2.rst71 reference tree [1] resets into EL1 before entering BL2 - see its
H A Drcar-gen3.rst71 reference tree [1] resets into EL1 before entering BL2 - see its
/rk3399_ARM-atf/docs/
H A Dporting-guide.rst1251 resets while booting from the active bank, the platform can then switch to boot
3334 resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
H A Dchange-log.md12638 - The version of the AEMv8 Base FVP used in this release resets the model
12773 - The version of the AEMv8 Base FVP used in this release resets the model
12911 - The version of the AEMv8 Base FVP used in this release resets the model