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Searched refs:read_mpidr_el1 (Results 1 – 25 of 84) sorted by relevance

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/rk3399_ARM-atf/plat/amlogic/axg/
H A Daxg_pm.c47 u_register_t mpidr = read_mpidr_el1(); in axg_system_reset()
68 u_register_t mpidr = read_mpidr_el1(); in axg_system_off()
108 axg_pm_set_reset_addr(read_mpidr_el1(), 0); in axg_pwr_domain_on_finish()
113 u_register_t mpidr = read_mpidr_el1(); in axg_pwr_domain_off()
142 axg_pm_reset(read_mpidr_el1(), 0); in axg_pwr_domain_pwr_down_wfi()
/rk3399_ARM-atf/drivers/nxp/interconnect/
H A Dls_cci.c19 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency()
31 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
H A Dls_ccn.c18 ccn_enter_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency()
30 ccn_exit_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
/rk3399_ARM-atf/plat/amlogic/gxl/
H A Dgxl_pm.c50 u_register_t mpidr = read_mpidr_el1(); in gxl_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in gxl_system_off()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxl_pwr_domain_on_finish()
149 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_off()
165 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_pwr_down_wfi()
/rk3399_ARM-atf/plat/amlogic/g12a/
H A Dg12a_pm.c50 u_register_t mpidr = read_mpidr_el1(); in g12a_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in g12a_system_off()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in g12a_pwr_domain_on_finish()
149 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_off()
166 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_pwr_down_wfi()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_cci.c32 cci_enable_snoop_dvm_reqs((unsigned int)MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
40 cci_disable_snoop_dvm_reqs((unsigned int)MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
H A Darm_ccn.c39 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
47 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_ccn.c36 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_enter_coherency()
44 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_exit_coherency()
/rk3399_ARM-atf/plat/brcm/common/
H A Dbrcm_ccn.c30 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_enter_coherency()
35 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_exit_coherency()
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmarvell_cci.c42 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_enter_coherency()
51 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_exit_coherency()
/rk3399_ARM-atf/plat/renesas/rcar_gen4/
H A Dplat_pm.c69 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish()
77 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_off()
90 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend()
115 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend_finish()
133 u_register_t mpidr = read_mpidr_el1(); in rcar_system_off()
184 u_register_t mpidr = read_mpidr_el1(); in rcar_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_pm.c53 uint64_t mpidr = read_mpidr_el1(); in fvp_cluster_pwrdwn_common()
82 mpidr = read_mpidr_el1(); in fvp_power_domain_on_finish_common()
184 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_off()
212 mpidr = read_mpidr_el1(); in fvp_pwr_domain_suspend()
234 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_suspend()
330 if ((read_mpidr_el1() & MPIDR_MT_MASK) == 0U) in fvp_node_hw_state()
/rk3399_ARM-atf/plat/amlogic/gxbb/
H A Dgxbb_pm.c77 gxbb_program_mailbox(read_mpidr_el1(), 0); in gxbb_system_off()
114 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_on_finish()
132 u_register_t mpidr = read_mpidr_el1(); in gxbb_pwr_domain_off()
152 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_pwr_down_wfi()
/rk3399_ARM-atf/plat/renesas/rcar_gen5/
H A Dplat_pm.c68 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish()
76 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_off()
85 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend()
104 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend_finish()
123 u_register_t mpidr = read_mpidr_el1(); in rcar_system_off()
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_cci.c27 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_enable()
32 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_disable()
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_pm.c86 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_on_finish()
94 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_off()
111 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_off()
190 u_register_t mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend()
266 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend_finish()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dimx8mq_psci.c46 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
62 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
90 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/rk3399_ARM-atf/plat/imx/imx93/
H A Dimx93_psci.c98 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_on_finish()
127 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
149 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_suspend()
174 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_suspend_finish()
/rk3399_ARM-atf/plat/renesas/common/
H A Dplat_pm.c81 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish()
99 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_off()
118 u_register_t mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend()
184 u_register_t mpidr = read_mpidr_el1(); in rcar_system_off()
280 u_register_t mpidr = read_mpidr_el1() & 0x0000ffffU; in rcar_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_psci_common.c110 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_on_finish()
121 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
150 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_suspend()
217 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_suspend_finish()
/rk3399_ARM-atf/plat/imx/imx8m/
H A Dimx8m_psci_common.c62 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
107 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
132 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/rk3399_ARM-atf/plat/arm/css/common/
H A Dcss_topology.c26 assert((read_mpidr_el1() & MPIDR_MT_MASK) != 0); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/drivers/arm/dsu/
H A Ddsu.c79 unsigned int cluster_pos = plat_cluster_id_by_mpidr(read_mpidr_el1()); in cluster_off_dsu_pmu_context_save()
131 unsigned int cluster_pos = plat_cluster_id_by_mpidr(read_mpidr_el1()); in cluster_on_dsu_pmu_context_restore()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dbrcm_pm_ops.c103 uint64_t mpidr = read_mpidr_el1(); in brcm_power_down_common()
154 scpi_set_brcm_power_state(read_mpidr_el1(), in brcm_scp_suspend()
172 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); in brcm_pwr_domain_off()
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Da3700_ea.c68 syndrome, read_mpidr_el1(), get_el_str(level)); in plat_ea_handler()

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