| /rk3399_ARM-atf/drivers/clk/ |
| H A D | clk.c | 14 static const struct clk_ops *ops; variable
18 assert((ops != NULL) && (ops->enable != NULL)); in clk_enable()
20 return ops->enable(id); in clk_enable()
25 assert((ops != NULL) && (ops->disable != NULL)); in clk_disable()
27 ops->disable(id); in clk_disable()
32 assert((ops != NULL) && (ops->get_rate != NULL)); in clk_get_rate()
34 return ops->get_rate(id); in clk_get_rate()
41 assert((ops != NULL) && (ops->set_rate != NULL)); in clk_set_rate()
44 return ops->set_rate(id, rate, orate); in clk_set_rate()
48 return ops->set_rate(id, rate, &lrate); in clk_set_rate()
[all …]
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| /rk3399_ARM-atf/drivers/gpio/ |
| H A D | gpio.c | 20 static const gpio_ops_t *ops; variable
24 assert(ops); in gpio_get_direction()
25 assert(ops->get_direction != 0); in gpio_get_direction()
28 return ops->get_direction(gpio); in gpio_get_direction()
33 assert(ops); in gpio_set_direction()
34 assert(ops->set_direction != 0); in gpio_set_direction()
38 ops->set_direction(gpio, direction); in gpio_set_direction()
43 assert(ops); in gpio_get_value()
44 assert(ops->get_value != 0); in gpio_get_value()
47 return ops->get_value(gpio); in gpio_get_value()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/ |
| H A D | mtk_pm.c | 25 int plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl *ops) in plat_pm_ops_setup_pwr() argument
27 if (!ops) { in plat_pm_ops_setup_pwr()
33 mtk_pm_ops.pwr_domain_suspend = ops->pwr_domain_suspend; in plat_pm_ops_setup_pwr()
37 mtk_pm_ops.pwr_domain_suspend_finish = ops->pwr_domain_suspend_finish; in plat_pm_ops_setup_pwr()
41 mtk_pm_ops.validate_power_state = ops->validate_power_state; in plat_pm_ops_setup_pwr()
45 mtk_pm_ops.get_sys_suspend_power_state = ops->get_sys_suspend_power_state; in plat_pm_ops_setup_pwr()
49 mtk_pm_ops.pwr_domain_pwr_down = ops->pwr_domain_pwr_down_wfi; in plat_pm_ops_setup_pwr()
56 int plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl *ops) in plat_pm_ops_setup_smp() argument
58 if (!ops) { in plat_pm_ops_setup_smp()
64 mtk_pm_ops.pwr_domain_on = ops->pwr_domain_on; in plat_pm_ops_setup_smp()
[all …]
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| H A D | mce.c | 77 arch_mce_ops_t *ops; member
85 .ops = &ari_mce_ops,
90 .ops = &ari_mce_ops,
95 .ops = &ari_mce_ops,
100 .ops = &ari_mce_ops,
105 .ops = &nvg_mce_ops,
110 .ops = &nvg_mce_ops,
152 return mce_cfg_table[cpuid].ops; in mce_get_curr_cpu_ops()
161 const arch_mce_ops_t *ops; in mce_command_handler() local
170 ops = mce_get_curr_cpu_ops(); in mce_command_handler()
[all …]
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| /rk3399_ARM-atf/drivers/mtd/spi-mem/ |
| H A D | spi_mem.c | 29 const struct spi_bus_ops *ops; member
90 const struct spi_bus_ops *ops = spi_slave.ops; in spi_mem_set_speed_mode() local
93 ret = ops->set_speed(spi_slave.max_hz); in spi_mem_set_speed_mode()
99 ret = ops->set_mode(spi_slave.mode); in spi_mem_set_speed_mode()
108 static int spi_mem_check_bus_ops(const struct spi_bus_ops *ops) in spi_mem_check_bus_ops() argument
112 if (ops->claim_bus == NULL) { in spi_mem_check_bus_ops()
117 if (ops->release_bus == NULL) { in spi_mem_check_bus_ops()
122 if (ops->exec_op == NULL) { in spi_mem_check_bus_ops()
127 if (ops->set_speed == NULL) { in spi_mem_check_bus_ops()
132 if (ops->set_mode == NULL) { in spi_mem_check_bus_ops()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/armv9_0/ |
| H A D | pwr_ctrl.c | 75 struct mtk_cpu_pm_ops *ops; member
81 .ops = NULL,
84 #define IS_CPUIDLE_FN_ENABLE(x) (imtk_cpu_pwr.ops && (imtk_cpu_pwr.fn_mask & (x)))
96 mret = imtk_cpu_pwr.ops->get_pstate( \
116 imtk_cpu_pwr.ops->mcusys_resume(state); in mcusys_pwr_on_common()
126 imtk_cpu_pwr.ops->mcusys_suspend(state); in mcusys_pwr_dwn_common()
136 imtk_cpu_pwr.ops->cluster_resume(state); in cluster_pwr_on_common()
142 imtk_cpu_pwr.ops->cluster_suspend(state); in cluster_pwr_dwn_common()
167 imtk_cpu_pwr.ops->cpu_resume(state); in cpu_pwr_resume()
174 imtk_cpu_pwr.ops->cpu_suspend(state); in cpu_pwr_suspend()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/armv8_2/ |
| H A D | pwr_ctrl.c | 63 struct mtk_cpu_pm_ops *ops; member
69 .ops = NULL,
72 #define IS_CPUIDLE_FN_ENABLE(x) ((mtk_cpu_pwr.ops != NULL) && ((mtk_cpu_pwr.fn_mask & x) != 0))
84 return mtk_cpu_pwr.ops->get_pstate(domain, psci_state, state); in get_mediatek_pstate()
114 mtk_cpu_pwr.ops->mcusys_resume(state); in armv8_2_mcusys_pwr_on_common()
126 mtk_cpu_pwr.ops->mcusys_suspend(state); in armv8_2_mcusys_pwr_dwn_common()
140 mtk_cpu_pwr.ops->cluster_resume(state); in armv8_2_cluster_pwr_on_common()
148 mtk_cpu_pwr.ops->cluster_suspend(state); in armv8_2_cluster_pwr_dwn_common()
184 mtk_cpu_pwr.ops->cpu_resume(state); in armv8_2_cpu_pwr_resume()
191 mtk_cpu_pwr.ops->cpu_suspend(state); in armv8_2_cpu_pwr_suspend()
[all …]
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| /rk3399_ARM-atf/drivers/delay_timer/ |
| H A D | generic_delay_timer.c | 19 static timer_ops_t ops; variable
53 ops.get_timer_value = generic_delay_get_timer_value; in generic_delay_timer_init_args()
54 ops.clk_mult = mult; in generic_delay_timer_init_args()
55 ops.clk_div = div; in generic_delay_timer_init_args()
56 ops.timeout_init_us = generic_delay_timeout_init_us; in generic_delay_timer_init_args()
57 ops.timeout_elapsed = generic_delay_timeout_elapsed; in generic_delay_timer_init_args()
59 timer_init(&ops); in generic_delay_timer_init_args()
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| /rk3399_ARM-atf/drivers/io/ |
| H A D | io_mtd.c | 116 io_mtd_ops_t *ops = &cur->dev_spec->ops; in mtd_add_extra_offset() local
119 if (ops->seek == NULL) { in mtd_add_extra_offset()
123 ret = ops->seek(cur->base, cur->pos, extra_offset); in mtd_add_extra_offset()
207 io_mtd_ops_t *ops; in mtd_read() local
214 ops = &cur->dev_spec->ops; in mtd_read()
215 assert(ops->read != NULL); in mtd_read()
223 ret = ops->read(cur->base + cur->pos + cur->extra_offset, buffer, in mtd_read()
246 io_mtd_ops_t *ops; in mtd_dev_open() local
257 ops = &(cur->dev_spec->ops); in mtd_dev_open()
258 if (ops->init != NULL) { in mtd_dev_open()
[all …]
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| H A D | io_block.c | 249 io_block_ops_t *ops; in block_read() local
269 ops = &(cur->dev_spec->ops); in block_read()
274 (ops->read != NULL)); in block_read()
317 request = ops->read(lba, buf->offset, request); in block_read()
361 io_block_ops_t *ops; in block_write() local
381 ops = &(cur->dev_spec->ops); in block_write()
386 (ops->read != NULL) && in block_write()
387 (ops->write != NULL)); in block_write()
446 request = ops->read(lba, buf->offset, request); in block_write()
471 request = ops->write(lba, buf->offset, request); in block_write()
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| /rk3399_ARM-atf/plat/mediatek/drivers/thermal/src/ |
| H A D | thermal_lvts.c | 475 struct platform_ops *ops = &lvts_data->ops; in lvts_init() local
494 ops->lvts_reset(lvts_data); in lvts_init()
496 if (ops->device_identification) in lvts_init()
497 ops->device_identification(lvts_data); in lvts_init()
499 if (ops->device_enable_and_init) in lvts_init()
500 ops->device_enable_and_init(lvts_data); in lvts_init()
503 if (ops->device_enable_auto_rck) in lvts_init()
504 ops->device_enable_auto_rck(lvts_data); in lvts_init()
506 if (ops->device_read_count_rc_n) in lvts_init()
507 ops->device_read_count_rc_n(lvts_data); in lvts_init()
[all …]
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| /rk3399_ARM-atf/plat/arm/board/juno/ |
| H A D | juno_pm.c | 10 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) in plat_arm_psci_override_pm_ops() argument
13 return css_scmi_override_pm_ops(ops); in plat_arm_psci_override_pm_ops()
15 return ops; in plat_arm_psci_override_pm_ops()
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| /rk3399_ARM-atf/drivers/arm/sp804/ |
| H A D | sp804_delay_timer.c | 41 void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops) in sp804_timer_ops_init() argument
44 assert(ops != 0 && ops->get_timer_value == sp804_get_timer_value); in sp804_timer_ops_init()
47 timer_init(ops); in sp804_timer_ops_init()
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| /rk3399_ARM-atf/lib/el3_runtime/ |
| H A D | cpu_data_array.c | 30 struct cpu_ops *ops; in cpu_data_init_cpu_ops() local
33 ops = get_cpu_ops_ptr(); in cpu_data_init_cpu_ops()
35 set_cpu_data(cpu_ops_ptr, ops); in cpu_data_init_cpu_ops()
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| /rk3399_ARM-atf/drivers/st/regulator/ |
| H A D | regulator_core.c | 33 if (rdev->desc->ops->lock != NULL) { in lock_driver()
34 rdev->desc->ops->lock(rdev->desc); in lock_driver()
40 if (rdev->desc->ops->unlock != NULL) { in unlock_driver()
41 rdev->desc->ops->unlock(rdev->desc); in unlock_driver()
123 if (rdev->desc->ops->set_state == NULL) { in __regulator_set_state()
127 return rdev->desc->ops->set_state(rdev->desc, state); in __regulator_set_state()
186 if (rdev->desc->ops->get_state == NULL) { in regulator_is_enabled()
192 ret = rdev->desc->ops->get_state(rdev->desc); in regulator_is_enabled()
226 if (rdev->desc->ops->set_voltage == NULL) { in regulator_set_voltage()
232 ret = rdev->desc->ops->set_voltage(rdev->desc, mvolt); in regulator_set_voltage()
[all …]
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| /rk3399_ARM-atf/drivers/nxp/timer/ |
| H A D | nxp_timer.c | 17 static timer_ops_t ops; variable
62 ops.get_timer_value = timer_get_value; in delay_timer_init_args()
63 ops.clk_mult = mult; in delay_timer_init_args()
64 ops.clk_div = div; in delay_timer_init_args()
66 timer_init(&ops); in delay_timer_init_args()
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| /rk3399_ARM-atf/plat/intel/soc/common/drivers/sdmmc/ |
| H A D | sdmmc.c | 25 static const struct mmc_ops *ops; variable
52 ret = ops->send_cmd(&cmd); in sdmmc_send_cmd()
116 assert((ops != NULL) && in sdmmc_write_blocks()
117 (ops->write != NULL) && in sdmmc_write_blocks()
122 ret = ops->prepare(lba, buf, size); in sdmmc_write_blocks()
155 ret = ops->write(lba, buf, size); in sdmmc_write_blocks()
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| /rk3399_ARM-atf/drivers/mmc/ |
| H A D | mmc.c | 26 static const struct mmc_ops *ops; variable
66 ret = ops->send_cmd(&cmd); in mmc_send_cmd()
172 ret = ops->prepare(0, (uintptr_t)&scr, sizeof(scr)); in mmc_sd_switch()
196 ret = ops->read(0, (uintptr_t)&scr, sizeof(scr)); in mmc_sd_switch()
253 return ops->set_ios(clk, width); in mmc_set_ios()
269 ret = ops->prepare(0, (uintptr_t)&mmc_ext_csd, in mmc_fill_device_info()
281 ret = ops->read(0, (uintptr_t)&mmc_ext_csd, in mmc_fill_device_info()
374 ret = ops->prepare(0, (uintptr_t)&sd_switch_func_status, in sd_switch()
389 return ops->read(0, (uintptr_t)&sd_switch_func_status, in sd_switch()
481 ops->init(); in mmc_enumerate()
[all …]
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| /rk3399_ARM-atf/plat/arm/board/corstone700/common/ |
| H A D | corstone700_pm.c | 19 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) in plat_arm_psci_override_pm_ops() argument
21 return ops; in plat_arm_psci_override_pm_ops()
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| /rk3399_ARM-atf/plat/arm/board/corstone1000/common/ |
| H A D | corstone1000_pm.c | 91 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
93 ops = &plat_arm_psci_pm_ops;
94 return ops;
83 plat_arm_psci_override_pm_ops(plat_psci_ops_t * ops) plat_arm_psci_override_pm_ops() argument
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/ |
| H A D | plat_pm_scmi.c | 238 const plat_psci_ops_t *plat_rcar_psci_override_pm_ops(plat_psci_ops_t *ops) in plat_rcar_psci_override_pm_ops() argument
257 ops->system_off = NULL; in plat_rcar_psci_override_pm_ops()
258 ops->system_reset = NULL; in plat_rcar_psci_override_pm_ops()
259 ops->get_sys_suspend_power_state = NULL; in plat_rcar_psci_override_pm_ops()
267 ops->get_sys_suspend_power_state = NULL; in plat_rcar_psci_override_pm_ops()
272 return ops; in plat_rcar_psci_override_pm_ops()
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| /rk3399_ARM-atf/plat/arm/board/morello/ |
| H A D | morello_bl31_setup.c | 35 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) in plat_arm_psci_override_pm_ops() argument
37 ops->pwr_domain_off = morello_pwr_domain_off; in plat_arm_psci_override_pm_ops()
38 return css_scmi_override_pm_ops(ops); in plat_arm_psci_override_pm_ops()
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| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rd1ae/ |
| H A D | rd1ae_bl31_setup.c | 25 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) in plat_arm_psci_override_pm_ops() argument
27 return css_scmi_override_pm_ops(ops); in plat_arm_psci_override_pm_ops()
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| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_storage.c | 155 boot_dev_spec.ops.read = SDMMC_READ_BLOCKS; in socfpga_io_setup()
156 boot_dev_spec.ops.write = SDMMC_WRITE_BLOCKS; in socfpga_io_setup()
167 nand_dev_spec.ops.init = cdns_nand_init_mtd; in socfpga_io_setup()
168 nand_dev_spec.ops.read = cdns_nand_read; in socfpga_io_setup()
169 nand_dev_spec.ops.write = NULL; in socfpga_io_setup()
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| /rk3399_ARM-atf/drivers/mtd/nand/ |
| H A D | raw_nand.c | 44 return rawnand_dev.ops->exec(&req); in nand_send_cmd()
57 return rawnand_dev.ops->exec(&req); in nand_send_addr()
70 return rawnand_dev.ops->exec(&req); in nand_send_wait()
84 return rawnand_dev.ops->exec(&req); in nand_read_data()
397 void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops) in nand_raw_ctrl_init() argument
399 rawnand_dev.ops = ops; in nand_raw_ctrl_init()
415 if ((rawnand_dev.ops->setup == NULL) || in nand_raw_init()
416 (rawnand_dev.ops->exec == NULL)) { in nand_raw_init()
442 rawnand_dev.ops->setup(rawnand_dev.nand_dev); in nand_raw_init()
|