xref: /rk3399_ARM-atf/drivers/arm/sp804/sp804_delay_timer.c (revision 18ff0b61bb205e01d2c4dba23f1be5fd1081c6b4)
1cc58b2d0SRyan Harkin /*
2*bde2836fSAmbroise Vincent  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3cc58b2d0SRyan Harkin  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
5cc58b2d0SRyan Harkin  */
6cc58b2d0SRyan Harkin 
7cc58b2d0SRyan Harkin #include <assert.h>
809d40e0eSAntonio Nino Diaz 
9*bde2836fSAmbroise Vincent #include <drivers/arm/sp804_delay_timer.h>
1009d40e0eSAntonio Nino Diaz #include <drivers/delay_timer.h>
1109d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
12cc58b2d0SRyan Harkin 
13cc58b2d0SRyan Harkin uintptr_t sp804_base_addr;
14cc58b2d0SRyan Harkin 
15cc58b2d0SRyan Harkin #define SP804_TIMER1_LOAD	(sp804_base_addr + 0x000)
16cc58b2d0SRyan Harkin #define SP804_TIMER1_VALUE	(sp804_base_addr + 0x004)
17cc58b2d0SRyan Harkin #define SP804_TIMER1_CONTROL	(sp804_base_addr + 0x008)
18cc58b2d0SRyan Harkin #define SP804_TIMER1_BGLOAD	(sp804_base_addr + 0x018)
19cc58b2d0SRyan Harkin 
20cc58b2d0SRyan Harkin #define TIMER_CTRL_ONESHOT	(1 << 0)
21cc58b2d0SRyan Harkin #define TIMER_CTRL_32BIT	(1 << 1)
22cc58b2d0SRyan Harkin #define TIMER_CTRL_DIV1		(0 << 2)
23cc58b2d0SRyan Harkin #define TIMER_CTRL_DIV16	(1 << 2)
24cc58b2d0SRyan Harkin #define TIMER_CTRL_DIV256	(2 << 2)
25cc58b2d0SRyan Harkin #define TIMER_CTRL_IE		(1 << 5)
26cc58b2d0SRyan Harkin #define TIMER_CTRL_PERIODIC	(1 << 6)
27cc58b2d0SRyan Harkin #define TIMER_CTRL_ENABLE	(1 << 7)
28cc58b2d0SRyan Harkin 
29cc58b2d0SRyan Harkin /********************************************************************
30cc58b2d0SRyan Harkin  * The SP804 timer delay function
31cc58b2d0SRyan Harkin  ********************************************************************/
sp804_get_timer_value(void)32cc58b2d0SRyan Harkin uint32_t sp804_get_timer_value(void)
33cc58b2d0SRyan Harkin {
34cc58b2d0SRyan Harkin 	return mmio_read_32(SP804_TIMER1_VALUE);
35cc58b2d0SRyan Harkin }
36cc58b2d0SRyan Harkin 
37cc58b2d0SRyan Harkin /********************************************************************
38cc58b2d0SRyan Harkin  * Initialize the 1st timer in the SP804 dual timer with a base
39cc58b2d0SRyan Harkin  * address and a timer ops
40cc58b2d0SRyan Harkin  ********************************************************************/
sp804_timer_ops_init(uintptr_t base_addr,const timer_ops_t * ops)41cc58b2d0SRyan Harkin void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops)
42cc58b2d0SRyan Harkin {
43cc58b2d0SRyan Harkin 	assert(base_addr != 0);
44cc58b2d0SRyan Harkin 	assert(ops != 0 && ops->get_timer_value == sp804_get_timer_value);
45cc58b2d0SRyan Harkin 
46cc58b2d0SRyan Harkin 	sp804_base_addr = base_addr;
47cc58b2d0SRyan Harkin 	timer_init(ops);
48cc58b2d0SRyan Harkin 
49cc58b2d0SRyan Harkin 	/* disable timer1 */
50cc58b2d0SRyan Harkin 	mmio_write_32(SP804_TIMER1_CONTROL, 0);
51cc58b2d0SRyan Harkin 	mmio_write_32(SP804_TIMER1_LOAD, UINT32_MAX);
52cc58b2d0SRyan Harkin 	mmio_write_32(SP804_TIMER1_VALUE, UINT32_MAX);
53cc58b2d0SRyan Harkin 
54cc58b2d0SRyan Harkin 	/* enable as a free running 32-bit counter */
55cc58b2d0SRyan Harkin 	mmio_write_32(SP804_TIMER1_CONTROL,
56cc58b2d0SRyan Harkin 			TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE);
57cc58b2d0SRyan Harkin }
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