| /rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/ |
| H A D | soc.h | 85 #define REG_W_MSK(bits_shift, msk) \ argument 86 ((msk) << ((bits_shift) + 16)) 87 #define REG_VAL_CLRBITS(val, bits_shift, msk) \ argument 88 ((val) & (~((msk) << bits_shift))) 89 #define REG_SET_BITS(bits, bits_shift, msk) \ argument 90 (((bits) & (msk)) << (bits_shift)) 91 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument 92 (REG_W_MSK(bits_shift, msk) | \ 93 REG_SET_BITS(bits, bits_shift, msk))
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| /rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/ |
| H A D | soc.h | 121 #define REG_W_MSK(bits_shift, msk) \ argument 122 ((msk) << ((bits_shift) + 16)) 123 #define REG_VAL_CLRBITS(val, bits_shift, msk) \ argument 124 (val & (~(msk << bits_shift))) 125 #define REG_SET_BITS(bits, bits_shift, msk) \ argument 126 (((bits) & (msk)) << (bits_shift)) 127 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument 128 (REG_W_MSK(bits_shift, msk) | \ 129 REG_SET_BITS(bits, bits_shift, msk))
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| /rk3399_ARM-atf/drivers/amlogic/crypto/ |
| H A D | sha_dma.c | 24 #define ASD_DESC_GET(x, msk, off) (((x) >> (off)) & (msk)) argument 25 #define ASD_DESC_SET(x, v, msk, off) \ argument 26 ((x) = ((x) & ~((msk) << (off))) | (((v) & (msk)) << (off)))
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| /rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/ |
| H A D | soc.h | 13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) argument
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) argument
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| /rk3399_ARM-atf/plat/rockchip/common/include/ |
| H A D | plat_private.h | 59 #define BITS_WITH_WMASK(bits, msk, shift)\ argument 60 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
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| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | imx8ulp_psci.c | 41 #define PMIC_CFG(v, m, msk) \ argument 45 .mode_msk = (msk), \ 65 #define SWT_BOARD(swt_on, msk) \ argument 68 .mask = (msk), \
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| /rk3399_ARM-atf/plat/rockchip/rk3576/ |
| H A D | rk3576_def.h | 13 #define BITS_WMSK(msk, shift) ((msk) << ((shift) + REG_MSK_SHIFT)) argument
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| /rk3399_ARM-atf/plat/imx/imx8ulp/upower/ |
| H A D | upower_soc_defs.h | 1019 uint8_t msk; /* Domain PMIC mode mask */ member 1055 return mode_cfg->B.msk; in get_pmic_mode_msk() 1079 uint8_t msk) in set_avd_pmic_mode_msk() argument 1081 get_pmic_mode_cfg(dom, cfg)->B.avd_msk = msk; in set_avd_pmic_mode_msk()
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| /rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/ |
| H A D | boot_init_dram.c | 684 uint32_t msk; in ddr_setval_s() local 693 msk = 0xffffffff; in ddr_setval_s() 695 msk = ((1U << len) - 1) << lsb; in ddr_setval_s() 698 tmp = (tmp & (~msk)) | ((val << lsb) & msk); in ddr_setval_s() 707 uint32_t msk; in ddr_getval_s() local 716 msk = 0xffffffff; in ddr_getval_s() 718 msk = ((1U << len) - 1); in ddr_getval_s() 721 tmp = (tmp >> lsb) & msk; in ddr_getval_s() 793 uint32_t msk; in ddrtbl_setval() local 803 msk = 0xffffffff; in ddrtbl_setval() [all …]
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| /rk3399_ARM-atf/drivers/st/usb/ |
| H A D | stm32mp1_usb.c | 330 uint32_t msk; in usb_dwc2_in_ep_int() local 333 msk = mmio_read_32(usb_base_addr + OTG_DIEPMSK); in usb_dwc2_in_ep_int() 335 msk |= ((emp >> epnum) << OTG_DIEPINT_TXFE_SHIFT) & OTG_DIEPINT_TXFE; in usb_dwc2_in_ep_int() 338 (epnum * OTG_DIEP_SIZE) + OTG_DIEPINT) & msk; in usb_dwc2_in_ep_int()
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| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/ |
| H A D | firewall.c | 631 __pmusramfunc void pmusram_fw_update_msk(uint32_t msk) in pmusram_fw_update_msk() argument 638 BITS_WITH_WMASK(msk, msk, 0)); in pmusram_fw_update_msk()
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| H A D | firewall.h | 494 __pmusramfunc void pmusram_fw_update_msk(uint32_t msk);
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| /rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/ |
| H A D | pmu.c | 527 #define CLK_MSK_GATING(msk, con) \ argument 528 mmio_write_32(CRU_BASE + (con), ((msk) << 16) | 0xffff) 529 #define CLK_MSK_UNGATING(msk, con) \ argument 530 mmio_write_32(CRU_BASE + (con), ((~(msk)) << 16) | 0xffff)
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/ |
| H A D | pmu.c | 269 static void pmu_qch_pwr_ctlr(uint32_t msk, uint32_t state) in pmu_qch_pwr_ctlr() argument 274 state = msk; in pmu_qch_pwr_ctlr() 277 BITS_WITH_WMASK(state, msk, 0)); in pmu_qch_pwr_ctlr() 279 while ((mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & msk) != state) { in pmu_qch_pwr_ctlr() 287 __func__, msk, state, in pmu_qch_pwr_ctlr()
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | stm32mp1_clk.c | 491 uint8_t msk; member 560 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 1024 (sel->msk << sel->src)) >> sel->src; in stm32mp1_clk_get_parent() 2376 usbreg_mask = (uint32_t)sel->msk << sel->src; in stm32mp1_clk_init() 2378 usbreg_mask |= (uint32_t)sel->msk << sel->src; in stm32mp1_clk_init() 2483 sel->msk; in get_parent_id_parent()
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