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Searched refs:mailbox (Results 1 – 25 of 30) sorted by relevance

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/rk3399_ARM-atf/plat/marvell/armada/a8k/common/ble/
H A Dble_main.c25 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in mailbox_clean() local
27 memset(mailbox, 0, PLAT_MARVELL_MAILBOX_SIZE); in mailbox_clean()
33 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in exec_ble_main() local
64 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || in exec_ble_main()
65 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) { in exec_ble_main()
70 (void (*)(void))mailbox[MBOX_IDX_ROM_EXIT_ADDR]; in exec_ble_main()
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmarvell_pm.c26 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in marvell_program_mailbox() local
33 ((PLAT_MARVELL_MAILBOX_BASE + sizeof(*mailbox)) <= in marvell_program_mailbox()
36 mailbox[MBOX_IDX_MAGIC] = MVEBU_MAILBOX_MAGIC_NUM; in marvell_program_mailbox()
37 mailbox[MBOX_IDX_SEC_ADDR] = address; in marvell_program_mailbox()
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/
H A Dplat_bl31_setup.c106 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in bl31_plat_arch_setup() local
119 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || in bl31_plat_arch_setup()
120 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) in bl31_plat_arch_setup()
140 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || in bl31_plat_arch_setup()
141 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) in bl31_plat_arch_setup()
H A Dplat_pm.c623 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in a8k_pwr_domain_suspend() local
632 mailbox[MBOX_IDX_SUSPEND_MAGIC] = MVEBU_MAILBOX_SUSPEND_STATE; in a8k_pwr_domain_suspend()
633 mailbox[MBOX_IDX_ROM_EXIT_ADDR] = (uintptr_t)&plat_marvell_exit_bootrom; in a8k_pwr_domain_suspend()
695 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in a8k_pwr_domain_suspend_finish() local
710 mailbox[MBOX_IDX_SUSPEND_MAGIC] = 0; in a8k_pwr_domain_suspend_finish()
711 mailbox[MBOX_IDX_ROM_EXIT_ADDR] = 0; in a8k_pwr_domain_suspend_finish()
/rk3399_ARM-atf/services/std_svc/spm/el3_spmc/
H A Dspmc.h101 struct mailbox { struct
185 struct mailbox mailbox; member
230 struct mailbox mailbox; member
293 struct mailbox *spmc_get_mbox_desc(bool secure_origin);
H A Dspmc_main.c126 struct mailbox *spmc_get_mbox_desc(bool secure_origin) in spmc_get_mbox_desc()
130 return &(spmc_get_current_sp_ctx()->mailbox); in spmc_get_mbox_desc()
132 return &(spmc_get_hyp_ctx()->mailbox); in spmc_get_mbox_desc()
831 struct mailbox *mbox; in rxtx_map_handler()
935 struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); in rxtx_unmap_handler()
1126 struct mailbox *mbox, in partition_info_populate_v1_0()
1173 struct mailbox *mbox; in partition_info_get_handler()
1590 struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); in rx_release_handler()
1665 struct mailbox *mb; in validate_secondary_ep()
1672 mb = &sp->mailbox; in validate_secondary_ep()
[all …]
H A Dspmc_shared_mem.c1019 static long spmc_ffa_fill_desc(struct mailbox *mbox, in spmc_ffa_fill_desc()
1226 struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); in spmc_ffa_mem_send()
1317 struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); in spmc_ffa_mem_frag_tx()
1530 struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); in spmc_ffa_mem_retrieve_req()
1803 struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); in spmc_ffa_mem_frag_rx()
1946 struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); in spmc_ffa_mem_relinquish()
/rk3399_ARM-atf/plat/hisilicon/hikey960/drivers/ipc/
H A Dhisi_ipc.c139 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_on_off() local
144 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_pm_on_off()
153 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_suspend() local
162 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_pm_suspend()
170 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_off() local
175 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_psci_system_off()
184 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_reset() local
189 hisi_ipc_send_cmd_with_ack(source, mailbox, cmdtype, cmdpara); in hisi_ipc_psci_system_reset()
/rk3399_ARM-atf/plat/arm/board/a5ds/
H A Da5ds_pm.c69 uintptr_t *mailbox = (void *)A5DS_TRUSTED_MAILBOX_BASE; in plat_setup_psci_ops() local
70 *mailbox = sec_entrypoint; in plat_setup_psci_ops()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_pm.c193 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; in plat_arm_program_trusted_mailbox() local
195 *mailbox = address; in plat_arm_program_trusted_mailbox()
202 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= in plat_arm_program_trusted_mailbox()
/rk3399_ARM-atf/bl32/tsp/
H A Dtsp_ffa_main.c43 static struct mailbox mailbox; variable
134 if (!memory_retrieve(&mailbox, &m, handle, source, test_receivers, in test_memory_send()
157 frag_length > (mailbox.rxtx_page_count * PAGE_SIZE)) { in test_memory_send()
168 memcpy(&mem_region_buffer[recv_length], mailbox.rx_buffer, in test_memory_send()
258 if (!memory_relinquish((struct ffa_mem_relinquish_descriptor *)mailbox.tx_buffer, in test_memory_send()
607 mailbox.tx_buffer = send_page; in tsp_main()
608 mailbox.rx_buffer = recv_page; in tsp_main()
609 mailbox.rxtx_page_count = 1; in tsp_main()
H A Dffa_helpers.h95 bool memory_retrieve(struct mailbox *mb,
H A Dffa_helpers.c143 bool memory_retrieve(struct mailbox *mb, in memory_retrieve()
/rk3399_ARM-atf/plat/qemu/qemu_sbsa/
H A Dsbsa_pm.c230 uintptr_t *mailbox = (uintptr_t *)PLAT_QEMU_TRUSTED_MAILBOX_BASE; in plat_setup_psci_ops() local
232 *mailbox = sec_entrypoint; in plat_setup_psci_ops()
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_pm.c233 uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE; in plat_setup_psci_ops() local
235 *mailbox = sec_entrypoint; in plat_setup_psci_ops()
/rk3399_ARM-atf/plat/ti/k3low/
H A Dplatform.mk22 drivers/ti/ipc/mailbox.c \
/rk3399_ARM-atf/plat/renesas/common/include/
H A Drcar_private.h16 typedef volatile struct mailbox { struct
/rk3399_ARM-atf/plat/renesas/rcar_gen5/include/
H A Drcar_private.h16 typedef volatile struct mailbox { struct
/rk3399_ARM-atf/fdts/
H A Dmorello-fvp.dts173 mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
H A Dmorello.dtsi52 mailbox: mhu@45000000 { label
H A Dmorello-soc.dts312 mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
/rk3399_ARM-atf/docs/plat/arm/fvp/
H A Dfvp-specific-configs.rst22 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
26 clear the mailbox at start-up.
33 dd if=/dev/zero of=mailbox.dat bs=1 count=8
35 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
40 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
/rk3399_ARM-atf/plat/rpi/rpi3/
H A Dplatform.mk81 drivers/rpi3/mailbox/rpi3_mbox.c \
/rk3399_ARM-atf/docs/plat/st/
H A Dstm32mp1.rst71 | SCMI mailbox | |
/rk3399_ARM-atf/docs/plat/
H A Drpi3.rst172 kernel. This mailbox is located at a different address in the AArch32 default
185 address to the mailbox so that the secondary CPUs jump to it and are recognised

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