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Searched refs:domain (Results 1 – 25 of 47) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/drivers/apusys/devapc/
H A Dapusys_dapc_v1.h117 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain) \ argument
118 APUSYS_APC_AO_ATTR(domain, \
124 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT(domain) \ argument
125 APUSYS_APC_AO_ATTR(domain, \
131 #define SLAVE_FORBID_EXCEPT_D5_NO_PROTECT(domain) \ argument
132 APUSYS_APC_AO_ATTR(domain, \
138 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT(domain) \ argument
139 APUSYS_APC_AO_ATTR(domain, \
145 #define SLAVE_FORBID_EXCEPT_D7_NO_PROTECT(domain) \ argument
146 APUSYS_APC_AO_ATTR(domain, \
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/rk3399_ARM-atf/plat/mediatek/drivers/emi_mpu/mt8188/
H A Demi_mpu_priv.h21 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
23 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
34 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
36 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/emi_mpu/
H A Demi_mpu.h23 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
25 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
38 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
40 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
/rk3399_ARM-atf/plat/imx/imx8ulp/upower/
H A Dupower_api.h227 int upwr_init(soc_domain_t domain, struct MU_t *muptr,
343 int upwr_xcp_sw_alarm(soc_domain_t domain, upwr_alarm_t code,
363 int upwr_xcp_set_ddr_retention(soc_domain_t domain, uint32_t enable,
383 int upwr_xcp_set_mipi_dsi_ena(soc_domain_t domain, uint32_t enable,
402 int upwr_xcp_get_mipi_dsi_ena(soc_domain_t domain, const upwr_callb callb);
420 int upwr_xcp_set_osc_mode(soc_domain_t domain, uint32_t osc_mode,
440 int upwr_xcp_set_rtd_use_ddr(soc_domain_t domain, uint32_t is_use_ddr,
459 int upwr_xcp_set_rtd_apd_llwu(soc_domain_t domain, uint32_t enable,
553 int upwr_pwm_dom_power_on(soc_domain_t domain, int boot_start,
582 int upwr_pwm_boot_start(soc_domain_t domain, const upwr_callb bootcallb);
[all …]
H A Dupower_api.c26 (hdr).domain = (uint32_t)pwr_domain; \
488 int upwr_init(soc_domain_t domain, struct MU_t *muptr, in upwr_init() argument
498 unsigned long dom_buffer_base = (domain == RTD_DOMAIN) ? UPWR_API_BUFFER_BASE : in upwr_init()
516 pwr_domain = domain; in upwr_init()
558 ping_msg.hdr.domain = pwr_domain; in upwr_init()
795 int upwr_xcp_sw_alarm(soc_domain_t domain, in upwr_xcp_sw_alarm() argument
812 txmsg.hdr.domain = (uint32_t)domain; in upwr_xcp_sw_alarm()
836 int upwr_xcp_set_ddr_retention(soc_domain_t domain, in upwr_xcp_set_ddr_retention() argument
853 txmsg.hdr.domain = (uint32_t)domain; in upwr_xcp_set_ddr_retention()
877 int upwr_xcp_set_mipi_dsi_ena(soc_domain_t domain, in upwr_xcp_set_mipi_dsi_ena() argument
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H A Dupower_soc_defs.h122 uint32_t domain : 16U; member
895 static inline unsigned int upwr_sizeof_pmode_cfg(uint32_t domain) in upwr_sizeof_pmode_cfg() argument
897 switch (domain) { in upwr_sizeof_pmode_cfg()
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_ammu.c31 uint8_t domain, uint8_t acp_en, uint8_t aw_clr, in apummu_set_segment_offset2() argument
39 APUMMU_BUILD_SEGMENT_OFFSET2(resv, domain, acp_en, aw_clr, aw_invalid, in apummu_set_segment_offset2()
129 uint8_t domain, uint8_t ns) in apummu_add_map() argument
151 apummu_set_segment_offset2(vsid_idx, seg_idx, 0, domain, in apummu_add_map()
159 uint8_t *domain, uint8_t *ns) in apummu_get_dns() argument
164 ret = sec_get_dns(engine_type, sec_level, domain, ns); in apummu_get_dns()
168 *domain = 7; in apummu_get_dns()
192 uint8_t domain, ns, seg; in apummu_add_apmcu_map() local
194 ret = apummu_get_dns(APUSYS_DEVICE_NUM, SEC_LEVEL_SECURE, &domain, &ns); in apummu_add_apmcu_map()
201 page_size, domain, ns); in apummu_add_apmcu_map()
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H A Dapusys_security_ctrl_perm_plat.c37 uint8_t *domain, uint8_t *ns) in sec_get_dns() argument
51 *domain = DOMAIN(NORMAL); in sec_get_dns()
57 *domain = DOMAIN(MVPU_SECURE); in sec_get_dns()
61 *domain = DOMAIN(MDLA_SECURE); in sec_get_dns()
65 *domain = DOMAIN(UP_SECURE); in sec_get_dns()
74 *domain = DOMAIN(SAPU); in sec_get_dns()
78 *domain = DOMAIN(AOV); in sec_get_dns()
H A Dapusys_ammu.h203 #define APUMMU_VSID_SEGMENT_08_DOMAIN(domain) \ argument
204 (((domain) & APUMMU_VSID_SEGMENT_08_DOMAIN_MASK) << APUMMU_VSID_SEGMENT_08_DOMAIN_SHIFT)
225 #define APUMMU_BUILD_SEGMENT_OFFSET2(resv, domain, acp_en, aw_clr, \ argument
230 (APUMMU_VSID_SEGMENT_08_DOMAIN(domain)) |\
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/emi_mpu/
H A Demi_mpu.h23 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
25 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
38 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
40 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.h15 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
16 int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);
21 int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
H A Dapupwr_clkctl.c115 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain) in apupwr_smc_acc_set_parent() argument
127 switch (domain) { in apupwr_smc_acc_set_parent()
134 acc_set = aacc_set[domain]; in apupwr_smc_acc_set_parent()
135 acc_clr = aacc_clr[domain]; in apupwr_smc_acc_set_parent()
200 int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain) in apupwr_smc_pll_set_rate() argument
215 switch (domain) { in apupwr_smc_pll_set_rate()
246 __func__, __LINE__, domain); in apupwr_smc_pll_set_rate()
251 anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()
265 switch (domain) { in apupwr_smc_pll_set_rate()
297 domain); in apupwr_smc_pll_set_rate()
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H A Dapupll.c90 static int32_t vd2pllidx(enum dvfs_voltage_domain domain) in vd2pllidx() argument
94 switch (domain) { in vd2pllidx()
110 ERROR("%s wrong voltage domain: %d\n", __func__, domain); in vd2pllidx()
507 int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain, in anpu_pll_set_rate() argument
513 pll_idx = vd2pllidx(domain); in anpu_pll_set_rate()
525 if (domain == V_VPU0 || domain == V_VPU1) { in anpu_pll_set_rate()
530 if (domain == V_MDLA0 || domain == V_MDLA1) { in anpu_pll_set_rate()
570 if (domain == V_VPU0 || domain == V_VPU1) { in anpu_pll_set_rate()
575 if (domain == V_MDLA0 || domain == V_MDLA1) { in anpu_pll_set_rate()
/rk3399_ARM-atf/docs/design/
H A Dpsci-pd-tree.rst13 It would be much simpler for the platform to describe its power domain tree
16 #. The generic PSCI code generates MPIDRs in order to populate the power domain
20 levels in the power domain tree to four.
23 mechanism used to populate the power domain topology tree.
25 #. The current arrangement of the power domain tree requires a binary search
27 domain node. During a power management operation, the tree is traversed from
36 #. The attributes of a core power domain differ from the attributes of power
37 domains at higher levels. For example, only a core power domain can be identified
39 performing a power management operation on the core power domain.
50 Describing a power domain tree
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/rk3399_ARM-atf/drivers/arm/gicv5/
H A Dgicv5_main.c42 static inline bool iwb_domain_supported(uint32_t idr0, uint8_t domain) in iwb_domain_supported() argument
44 return (EXTRACT(IWB_IDR0_DOMAINS, idr0) & (1U << domain)) != 0U; in iwb_domain_supported()
54 write_iwb_wdomainr(base_addr, reg_index, val | wire.domain << reg_offset); in iwb_configure_domainr()
88 assert(iwb_domain_supported(idr0, config->wires[i].domain)); in iwb_enable()
101 static void irs_configure_wire(uintptr_t base_addr, uint32_t wire, uint8_t domain) in irs_configure_wire() argument
106 write_irs_spi_domainr(base_addr, domain); in irs_configure_wire()
133 irs_configure_wire(base_addr, config->spis[i].id, config->spis[i].domain); in irs_enable()
136 if (config->spis[i].domain == INTDMN_EL3) { in irs_enable()
/rk3399_ARM-atf/docs/design_documents/
H A Dpsci_osi_mode.rst17 A power domain topology is a logical hierarchy of power domains in a system that
25 coordinating its children nodes. For example, in a system with a power domain
26 that encompasses a shared cache, and a separate power domain for each core that
28 shared cache power domain can be powered down.
224 * The requested level in the power domain topology to enter a low-power
412 power-domain-names = "psci";
420 power-domain-names = "psci";
434 domain-idle-states {
435 CLUSTER_STOP: core-power-domain {
436 compatible = "domain-idle-state";
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/emi_mpu/
H A Demi_mpu.h51 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4) argument
53 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4) argument
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/security_ctrl/
H A Dapusys_security_ctrl_perm.h22 uint8_t *domain, uint8_t *ns);
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm.c337 static unsigned int cpupm_get_pstate(enum mt_cpupm_pwr_domain domain, in cpupm_get_pstate() argument
350 if (domain == CPUPM_PWR_OFF) { in cpupm_get_pstate()
352 } else if (domain == CPUPM_PWR_ON) { in cpupm_get_pstate()
356 __func__, __LINE__, domain); in cpupm_get_pstate()
/rk3399_ARM-atf/include/drivers/arm/
H A Dgicv5.h170 .domain = (_domain), \
178 uint8_t domain:2; member
/rk3399_ARM-atf/plat/mediatek/drivers/thermal/mt8189/
H A Dsoc_temp_lvts.c437 lvts_data->domain[i].reset_set_bitnum); in mt8189_lvts_reset()
438 mmio_write_32((lvts_data->domain[i].reset_base + in mt8189_lvts_reset()
439 lvts_data->domain[i].reset_set_offset), in mt8189_lvts_reset()
445 lvts_data->domain[i].reset_clr_bitnum); in mt8189_lvts_reset()
446 mmio_write_32((lvts_data->domain[i].reset_base + in mt8189_lvts_reset()
447 lvts_data->domain[i].reset_clr_offset), in mt8189_lvts_reset()
721 .domain = mt8189_domain_settings,
/rk3399_ARM-atf/plat/mediatek/drivers/thermal/inc/
H A Dthermal_lvts.h28 (lvts_data->domain[lvts_data->tc[tc_id].domain_index].base \
178 struct power_domain *domain; member
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/devapc/
H A Ddevapc.c32 static void set_master_domain(uint32_t master_index, enum MASK_DOM domain) in set_master_domain() argument
43 set_bit = domain << (4 * domain_index); in set_master_domain()
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/
H A Dfirewall.c72 uint32_t domain[FW_SGRF_MST_DOMAIN_CON_CNT]; member
204 fw_config_buf.domain[mst_id >> 3] &= ~(0xf << sft); in fw_buf_sys_mst_dm_cfg()
205 fw_config_buf.domain[mst_id >> 3] |= (dm_id & 0xf) << sft; in fw_buf_sys_mst_dm_cfg()
449 fw_config_buf.domain[i] = 0x0; in fw_domain_init()
535 fw_config_buf.domain[i]); in fw_config_buf_flush()
/rk3399_ARM-atf/docs/components/
H A Dmpmm.rst7 assist in |SoC| processor power domain dynamic power budgeting and limit the

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