| /rk3399_ARM-atf/include/dt-bindings/clock/ |
| H A D | stm32mp21-clksrc.h | 69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
70 ((div_id) << DIV_ID_SHIFT |\
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| H A D | stm32mp25-clksrc.h | 69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
70 ((div_id) << DIV_ID_SHIFT |\
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| H A D | stm32mp13-clksrc.h | 68 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
69 ((div_id) << DIV_ID_SHIFT |\
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| H A D | stm32mp15-clksrc.h | 42 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
43 ((div_id) << DIV_ID_SHIFT) |\
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32-core.h | 190 int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id,
197 int div_id,
209 uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id);
210 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value);
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| H A D | clk-stm32-core.c | 728 uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id) in clk_stm32_div_get_value() argument
730 const struct div_cfg *divider = &priv->div[div_id]; in clk_stm32_div_get_value()
740 int div_id, in _clk_stm32_divider_recalc() argument
743 const struct div_cfg *divider = &priv->div[div_id]; in _clk_stm32_divider_recalc()
744 uint32_t val = clk_stm32_div_get_value(priv, div_id); in _clk_stm32_divider_recalc()
768 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) in clk_stm32_set_div() argument
775 if (div_id >= priv->nb_div) { in clk_stm32_set_div()
779 divider = &priv->div[div_id]; in clk_stm32_set_div()
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| H A D | stm32mp1_clk.c | 267 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) in clk_stm32_set_div() argument
274 if (div_id >= priv->nb_div) { in clk_stm32_set_div()
278 divider = &priv->div[div_id]; in clk_stm32_set_div()
1083 enum stm32mp1_div_id div_id) in stm32mp1_read_pll_freq() argument
1089 if (div_id >= _DIV_NB) { in stm32mp1_read_pll_freq()
1094 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; in stm32mp1_read_pll_freq()
2054 uint32_t div_id, div_n; in stm32_clk_dividers_configure() local
2059 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT; in stm32_clk_dividers_configure()
2062 ret = clk_stm32_set_div(priv, div_id, div_n); in stm32_clk_dividers_configure()
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| H A D | clk-stm32mp13.c | 1092 int div_id, div_n; in stm32_clk_dividers_configure() local
1097 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT; in stm32_clk_dividers_configure()
1100 ret = clk_stm32_set_div(priv, div_id, div_n); in stm32_clk_dividers_configure()
1783 uint8_t div_id; member
1792 return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate); in clk_stm32_composite_recalc_rate()
1833 .div_id = (_div_id),\
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| H A D | clk-stm32mp2.c | 2111 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; in stm32_clk_configure_div() local
2114 return clk_stm32_set_div(priv, div_id, div_n); in stm32_clk_configure_div()
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | pm_api_clock.h | 296 uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id);
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| H A D | zynqmp_pm_api_sys.c | 1331 enum pm_clock_div_id div_id; in pm_clock_setdivider() local
1352 div_id = PM_CLOCK_DIV0_ID; in pm_clock_setdivider()
1355 div_id = PM_CLOCK_DIV1_ID; in pm_clock_setdivider()
1363 PM_PACK_PAYLOAD4(payload, flag, PM_CLOCK_SETDIVIDER, clock_id, div_id, val); in pm_clock_setdivider()
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| H A D | pm_api_clock.c | 3123 uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id) in pm_clock_has_div() argument
3136 if (div_id == PM_CLOCK_DIV0_ID) { in pm_clock_has_div()
3141 if (div_id == PM_CLOCK_DIV1_ID) { in pm_clock_has_div()
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