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Searched refs:bank (Results 1 – 25 of 39) sorted by relevance

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/rk3399_ARM-atf/drivers/st/gpio/
H A Dstm32_gpio.c28 static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
36 static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) in ckeck_gpio_bank() argument
39 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank); in ckeck_gpio_bank()
102 uint32_t bank; in dt_set_gpio_config() local
114 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; in dt_set_gpio_config()
156 bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node); in dt_set_gpio_config()
168 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); in dt_set_gpio_config()
170 set_gpio(bank, pin, mode, type, speed, pull, od, alternate, status); in dt_set_gpio_config()
225 static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type, in set_gpio() argument
229 uintptr_t base = stm32_get_gpio_bank_base(bank); in set_gpio()
[all …]
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_private.c111 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) in stm32_get_gpio_bank_base() argument
114 assert(bank <= GPIO_BANK_I); in stm32_get_gpio_bank_base()
117 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_base()
121 assert(bank <= GPIO_BANK_K); in stm32_get_gpio_bank_base()
124 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); in stm32_get_gpio_bank_base()
127 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) in stm32_get_gpio_bank_offset() argument
130 assert(bank <= GPIO_BANK_I); in stm32_get_gpio_bank_offset()
133 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_offset()
137 assert(bank <= GPIO_BANK_K); in stm32_get_gpio_bank_offset()
140 return bank * GPIO_BANK_OFFSET; in stm32_get_gpio_bank_offset()
[all …]
H A Dstm32mp1_shared_resources.c111 static unsigned int get_gpio_nbpin(unsigned int bank) in get_gpio_nbpin() argument
113 if (bank != GPIO_BANK_Z) { in get_gpio_nbpin()
114 int count = fdt_get_gpio_bank_pin_count(bank); in get_gpio_nbpin()
313 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin) in stm32mp_register_secure_gpio() argument
315 switch (bank) { in stm32mp_register_secure_gpio()
320 ERROR("GPIO bank %u cannot be secured\n", bank); in stm32mp_register_secure_gpio()
325 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin) in stm32mp_register_non_secure_gpio() argument
327 switch (bank) { in stm32mp_register_non_secure_gpio()
336 static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank) in stm32mp_gpio_bank_is_non_secure() argument
343 if (bank != GPIO_BANK_Z) { in stm32mp_gpio_bank_is_non_secure()
[all …]
/rk3399_ARM-atf/plat/st/common/include/
H A Dstm32mp_shared_resources.h33 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin);
34 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin);
48 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, in stm32mp_register_secure_gpio()
53 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, in stm32mp_register_non_secure_gpio()
H A Dstm32mp_common.h97 uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
98 unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
99 uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
100 bool stm32_gpio_is_secure_at_reset(unsigned int bank);
103 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
H A Dstm32mp_dt.h44 int fdt_get_gpio_bank_pin_count(unsigned int bank);
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dstm32mp2_private.c110 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) in stm32_get_gpio_bank_base() argument
112 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_base()
116 assert(bank <= GPIO_BANK_K); in stm32_get_gpio_bank_base()
118 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); in stm32_get_gpio_bank_base()
121 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) in stm32_get_gpio_bank_offset() argument
123 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_offset()
127 assert(bank <= GPIO_BANK_K); in stm32_get_gpio_bank_offset()
129 return bank * GPIO_BANK_OFFSET; in stm32_get_gpio_bank_offset()
132 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) in stm32_get_gpio_bank_clock() argument
134 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_clock()
[all …]
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32_gpio.h60 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
61 void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
68 void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level);
69 enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin);
71 void set_gpio_config(uint32_t bank, uint32_t pin, uint32_t config, uint8_t status);
/rk3399_ARM-atf/drivers/st/bsec/
H A Dbsec3.c73 uint32_t bank = otp_bank(otp); in is_fuse_shadowed() local
77 bank_value = mmio_read_32(BSEC_BASE + BSEC_SFSR(bank)); in is_fuse_shadowed()
341 uint32_t bank = otp_bank(otp); in bsec_set_sr_lock() local
348 return bsec_lock_register_set(BSEC_SRLOCK(bank), otp_mask); in bsec_set_sr_lock()
359 uint32_t bank = otp_bank(otp); in bsec_read_sr_lock() local
367 *value = bsec_lock_register_get(BSEC_SRLOCK(bank), otp_mask); in bsec_read_sr_lock()
379 uint32_t bank = otp_bank(otp); in bsec_set_sw_lock() local
386 return bsec_lock_register_set(BSEC_SWLOCK(bank), otp_mask); in bsec_set_sw_lock()
397 uint32_t bank = otp_bank(otp); in bsec_read_sw_lock() local
405 *value = bsec_lock_register_get(BSEC_SWLOCK(bank), otp_mask); in bsec_read_sw_lock()
[all …]
H A Dbsec2.c208 uint32_t bank = otp_bank_offset(otp); in bsec_check_error() local
210 if ((mmio_read_32(BSEC_BASE + BSEC_ERROR_OFF + bank) & bit) != 0U) { in bsec_check_error()
218 if ((mmio_read_32(BSEC_BASE + BSEC_DISTURBED_OFF + bank) & bit) != 0U) { in bsec_check_error()
576 uint32_t bank = otp_bank_offset(otp); in bsec_set_sr_lock() local
588 mmio_write_32(BSEC_BASE + BSEC_SRLOCK_OFF + bank, otp_mask); in bsec_set_sr_lock()
602 uint32_t bank = otp_bank_offset(otp); in bsec_read_sr_lock() local
610 bank_value = mmio_read_32(BSEC_BASE + BSEC_SRLOCK_OFF + bank); in bsec_read_sr_lock()
624 uint32_t bank = otp_bank_offset(otp); in bsec_set_sw_lock() local
636 mmio_write_32(BSEC_BASE + BSEC_SWLOCK_OFF + bank, otp_mask); in bsec_set_sw_lock()
650 uint32_t bank = otp_bank_offset(otp); in bsec_read_sw_lock() local
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c181 uint32_t bank = GET_GPIO_BANK(gpio); in get_pull() local
188 assert(bank <= info->max_bank); in get_pull()
191 val = (mmio_read_32(info->pull_base + 4 * bank) >> (id * 2)) & GPIO_P_MASK; in get_pull()
194 return pull_type_hw2sw[info->pull_enc[bank]][val]; in get_pull()
200 uint32_t bank = GET_GPIO_BANK(gpio); in set_pull() local
207 assert(bank <= info->max_bank); in set_pull()
209 uint8_t val = pull_type_sw2hw[info->pull_enc[bank]][pull]; in set_pull()
215 info->pull_base + 4 * bank, in set_pull()
/rk3399_ARM-atf/fdts/
H A Dstm32mp251.dtsi373 st,bank-name = "GPIOA";
384 st,bank-name = "GPIOB";
395 st,bank-name = "GPIOC";
406 st,bank-name = "GPIOD";
417 st,bank-name = "GPIOE";
428 st,bank-name = "GPIOF";
439 st,bank-name = "GPIOG";
450 st,bank-name = "GPIOH";
461 st,bank-name = "GPIOI";
472 st,bank-name = "GPIOJ";
[all …]
H A Dstm32mp151.dtsi549 st,bank-name = "GPIOA";
560 st,bank-name = "GPIOB";
571 st,bank-name = "GPIOC";
582 st,bank-name = "GPIOD";
593 st,bank-name = "GPIOE";
604 st,bank-name = "GPIOF";
615 st,bank-name = "GPIOG";
626 st,bank-name = "GPIOH";
637 st,bank-name = "GPIOI";
648 st,bank-name = "GPIOJ";
[all …]
H A Dstm32mp131.dtsi480 st,bank-name = "GPIOA";
492 st,bank-name = "GPIOB";
504 st,bank-name = "GPIOC";
516 st,bank-name = "GPIOD";
528 st,bank-name = "GPIOE";
540 st,bank-name = "GPIOF";
552 st,bank-name = "GPIOG";
564 st,bank-name = "GPIOH";
576 st,bank-name = "GPIOI";
H A Dcorstone700_fvp.dts23 bank-width = <4>;
H A Dn1sdp-single-chip.dts23 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
/rk3399_ARM-atf/drivers/st/fmc/
H A Dstm32_fmc2_nand.c799 uint8_t bank; in stm32_fmc2_init() local
830 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
831 if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) { in stm32_fmc2_init()
834 bank_assigned |= BIT(bank); in stm32_fmc2_init()
835 bank_address[bank] = fdt32_to_cpu(*(cuint + 2)); in stm32_fmc2_init()
861 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
862 if (bank >= MAX_BANK) { in stm32_fmc2_init()
866 bank_address[bank]; in stm32_fmc2_init()
868 bank = fdt32_to_cpu(*(cuint + 3)); in stm32_fmc2_init()
869 if (bank >= MAX_BANK) { in stm32_fmc2_init()
[all …]
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/
H A Dboot_init_dram_regdef.h24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_rstd.c33 int bank = reset_domain->id / 16; in rk3588_reset_explicit() local
36 mmio_write_32(SCRU_BASE + CRU_SOFTRST_CON(bank), in rk3588_reset_explicit()
/rk3399_ARM-atf/plat/st/common/
H A Dstm32mp_dt.c375 int fdt_get_gpio_bank_pin_count(unsigned int bank) in fdt_get_gpio_bank_pin_count() argument
381 pinctrl_node = stm32_get_gpio_bank_pinctrl_node(fdt, bank); in fdt_get_gpio_bank_pin_count()
386 bank_offset = stm32_get_gpio_bank_offset(bank); in fdt_get_gpio_bank_pin_count()
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c176 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
192 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
195 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
191 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
194 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
220 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
223 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/docs/components/
H A Dfirmware-update.rst49 An active bank stores running firmware, whereas an update bank contains
52 Once Firmwares are updated in the update bank of the non-volatile
53 storage, then ``Update Agent`` marks the update bank as the active bank,
67 By default, the platform uses the active bank of non-volatile storage to boot
80 If the platform fails to boot from active bank due to any reasons such
85 bank.
88 bank (e.g. due to ageing effect of non-volatile storage) then the platform can
/rk3399_ARM-atf/docs/plat/nxp/
H A Dnxp-layerscape.rst209 - DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h i…
342 Notes: ls1028ardb has no flexspi-Nor Alt Bank, so use "sf probe 0:0" for current bank.
360 -- Then reset to alternate bank to boot up ATF.
418 -- Then reset to alternate bank to boot up ATF.

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