| /rk3399_ARM-atf/docs/components/ |
| H A D | romlib-design.rst | 1 Library at ROM
4 This document provides an overview of the "library at ROM" implementation in
10 The "library at ROM" feature allows platforms to build a library of functions to
12 ROM. The "library at ROM" contains a jump table with the list of functions that
13 are placed in ROM. The capabilities of the "library at ROM" are:
29 Library at ROM is described by an index file with the list of functions to be
37 function -- Name of the function to be placed in library at ROM
60 When invoking a function of the "library at ROM", the calling sequence is as
63 BL image --> wrapper function --> jump table entry --> library at ROM
66 wrappers refer to the jump table to call the "library at ROM" functions. The
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| H A D | secure-partition-manager.rst | 46 can be selected at build time.
52 SPMC) residing at different exception levels. To permit the FF-A specification
53 adoption and a smooth migration, the SPMD supports an SPMC residing either at
56 - The SPMD is located at EL3 and mainly relays the FF-A protocol from NWd
72 support for an FF-A based SPM where the SPMD is located at EL3 and the
73 SPMC located at S-EL1, S-EL2 or EL3:
79 level to being at S-EL2. It defaults to enabled (value 1) when
82 at EL3. If neither ``SPMD_SPM_AT_SEL2`` or ``SPMC_AT_EL3`` are enabled the
85 and exhaustive list of registers is visible at `[4]`_.
87 when SPMC at EL3 support is enabled.
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| H A D | context-management-library.rst | 6 and their accessibility from other components at EL3.
27 to preserve the state of the CPU at the next lower exception level (EL) in a given
32 In a trusted system at any instance, a given CPU could be executing in one of the
70 state called root. EL3 firmware now runs at Root World and thereby is
78 Context Management library running at EL3 should only initialize and monitor the
96 to detect its presence at runtime. This helps dispatchers to select the desired
101 TF-A supports four states for feature enablement at EL3, to make them available
120 existence will be checked at runtime. Default on dynamic platforms (example: FVP).
144 it is essential to know its presence at compile time. Refer to ``ENABLE_FEAT``
285 at compile time as shown below.
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| H A D | ven-el3-service.rst | 70 For example adding an new monitor service at 0x30, Debugfs starts at 0x10 and PMF
71 starts at 0x20 next one will start at 0x30, this will need a update to minor version.
77 allows callers to retrieve timestamps captured at various paths in TF-A
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| H A D | realm-management-extension.rst | 43 In a typical TF-A boot flow, BL2 runs at Secure-EL1. However when RME is
44 enabled, TF-A runs in the Root world at EL3. Therefore, the boot flow is
45 modified to run BL2 at EL3 when RME is enabled. In addition to this, a
51 1. BL1 loads and executes BL2 at EL3
77 This contract is defined in the `RMM`_ Boot Interface, which can be found at
81 to `RMM`_. This can be found at :ref:`runtime_services_and_interface`.
85 TRP is a small test payload that runs at R-EL2 and implements a subset of
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| /rk3399_ARM-atf/docs/plat/ |
| H A D | mt8196.rst | 7 Cortex-A720 can operate at up to 2.1 GHz.
8 Cortex-X4 can operate at up to 2.8 GHz.
9 Cortex-X925 can operate at up to 3.6 GHz.
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| H A D | mt8189.rst | 7 Cortex-A55 can operate at up to 2.0 GHz.
8 Cortex-A78 can operate at up to 3.0 GHz.
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| H A D | mt8186.rst | 6 Cortex-A76 can operate at up to 2.05 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| H A D | mt8192.rst | 6 Cortex-A76 can operate at up to 2.2 GHz.
7 Cortex-A55 can operate at up to 2 GHz.
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| H A D | mt8195.rst | 6 Cortex-A78 can operate at up to 2.6 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| H A D | mt8188.rst | 6 Cortex-A78 can operate at up to 2.6 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| H A D | poplar.rst | 12 video at 60 frames per second.
116 LOADER: CPU0 executes at 0x000ce000
124 INFO: Loading image id=1 at address 0xe9000
125 INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
132 INFO: Loading image id=3 at address 0x129000
133 INFO: Image id=3 loaded at address 0x129000, size = 0x8038
135 INFO: Loading image id=5 at address 0x37000000
136 INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
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| H A D | ast2700.rst | 5 Each core operates at 1.6GHz.
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| H A D | intel-stratix10.rst | 78 INFO: Loading image id=3 at address 0xffe1c000
81 INFO: Loading image id=5 at address 0x50000
94 UEFI firmware (version 1.0 built at 11:26:18 on Nov 7 2018)
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| /rk3399_ARM-atf/docs/perf/ |
| H A D | performance-monitoring-unit.rst | 18 The PMU makes 32 counters available at all privilege levels:
50 ``PMCR`` registers. These can be accessed at all privilege levels.
79 - If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
84 - If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
91 - If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
98 at Secure EL2.
104 - If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
121 In other words, the counter will not increment at any privilege level or
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| /rk3399_ARM-atf/fdts/ |
| H A D | arm_fpga.dts | 8 * populated accordingly at runtime.
34 /* /cpus node will be added by BL31 at runtime. */
54 /* This node will be removed at runtime on cores without SPE. */
97 /* The GICR size will be adjusted at runtime to match the cores. */
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| /rk3399_ARM-atf/docs/plat/marvell/armada/ |
| H A D | build.rst | 22 For example: if U-Boot project (and its images) is located at ``~/project/u-boot``,
99 for SRAM address range at BL31 execution stage with window target set to DRAM-0.
233 - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
234 - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
235 - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
236 - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
238 Look at Armada37x0 chip package marking on board to identify correct CPU frequency.
260 Image needs to be stored at disk LBA 0 or at disk partition with
261 MBR type 0x4d (ASCII 'M' as in Marvell) or at disk partition with
292 CZ.NIC's Armada 3720 Secure Firmware is available at website:
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| /rk3399_ARM-atf/docs/design/ |
| H A D | alt-boot-flows.rst | 7 On a pre-production system, the ability to execute arbitrary, bare-metal code at
52 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
56 used. The infinite loop that it introduces in BL1 stops execution at the right
71 is complete, TF-A simply jumps to a BL33 base address provided at build time.
75 without a BL33 and prepare to jump to a BL33 image loaded at address
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| /rk3399_ARM-atf/docs/plat/arm/fvp/ |
| H A D | fvp-specific-configs.rst | 4 When Firmware Update (FWU) is enabled there are at least 2 new images
22 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
26 clear the mailbox at start-up.
35 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
47 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
75 required initrd properties are injected in to the device tree blob (DTB) at
121 error by the kernel at runtime. This error can be ignored because initrd's
132 For example, if the kernel is loaded at ``0x80080000`` the firmware can be
158 end properties into the DTB (HW_CONFIG) at build time which is then stored by
239 - Use this configuration at your own discretion, understanding that the design
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| /rk3399_ARM-atf/services/spd/tlkd/ |
| H A D | tlkd_common.c | 38 int at = type & AT_MASK; in tlkd_va_translate() local
39 switch (at) { in tlkd_va_translate()
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| /rk3399_ARM-atf/plat/arm/board/fvp/fdts/ |
| H A D | fvp_fw_config.dts | 34 * Load SoC and TOS firmware configs at the base of
37 * is loaded at base of DRAM.
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| /rk3399_ARM-atf/docs/ |
| H A D | architecture_features.rst | 6 at EL3, some demand explicit configuration of EL3 control registers to enable their use at lower
464 ENABLE_FEAT_* = 0: Feature is unconditionally disabled at compile time.
465 ENABLE_FEAT_* = 1: Feature is unconditionally enabled at compile time.
467 feature present at runtime.
478 but its existence will be checked at runtime, so it works on CPUs with or
480 multiple different CPUs, or where the CPU is configured at runtime, like in
488 a) a feature is added to the architecture and it includes controls at EL3
508 add it to the appropriate list at the top of the same file.
541 for lower ELs, access must be enabled for at least NS world, preferably all
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| /rk3399_ARM-atf/docs/plat/arm/arm_fpga/ |
| H A D | index.rst | 20 be auto-detected at runtime.
23 across the various images, this is detected at runtime by BL31.
45 so it must describe at least the UART and a GICv3 interrupt controller.
87 components at their respective load addresses. In addition to this file
88 you need at least a BL33 payload (typically a Linux kernel image), optionally
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| /rk3399_ARM-atf/docs/security_advisories/ |
| H A D | security-advisory-tfv-3.rst | 5 | Title | RO memory is always executable at AArch64 Secure EL1 |
15 | Affected | executing at AArch64 Secure EL1 |
34 This feature does not work correctly for AArch64 images executing at Secure EL1.
62 permissions but always leaves the memory as executable at Secure EL1.
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| /rk3399_ARM-atf/docs/plat/qti/ |
| H A D | chrome.rst | 41 QTISELIB for SC7180 is available at
43 QTISELIB for SC7280 is available at
|