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Searched refs:SYSMGR_ECC_DDR0_MASK (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_system_manager.h28 #define SYSMGR_ECC_DDR0_MASK BIT(16) macro
H A Dsocfpga_sip_svc.h167 SYSMGR_ECC_DDR0_MASK |\
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Ds10_system_manager.h190 #define SYSMGR_ECC_DDR0_MASK BIT(16) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_system_manager.h191 #define SYSMGR_ECC_DDR0_MASK BIT(16) macro
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dn5x_system_manager.h194 #define SYSMGR_ECC_DDR0_MASK BIT(16) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_system_manager.h224 #define SYSMGR_ECC_DDR0_MASK BIT(16) macro