| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | imx8_psci.c | 45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
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| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | plat_pm.c | 24 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
229 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()
265 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()
286 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_on_finish()
330 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/ |
| H A D | plat_psci_handlers.c | 65 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state()
112 if (lvl == MPIDR_AFFLVL1) in tegra_soc_get_target_pwr_state()
117 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { in tegra_soc_get_target_pwr_state()
175 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state()
200 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; in tegra_soc_pwr_domain_suspend()
507 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in tegra_soc_pwr_domain_on_finish()
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| /rk3399_ARM-atf/plat/mediatek/include/armv9/ |
| H A D | arch_def.h | 16 #define PLAT_MAX_RET_STATE MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/imx/imx8m/include/ |
| H A D | imx8m_psci.h | 11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
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| /rk3399_ARM-atf/plat/amlogic/gxl/include/ |
| H A D | platform_def.h | 27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/marvell/armada/a8k/common/mss/ |
| H A D | mss_pm_ipc.c | 45 MPIDR_AFFLVL1]); in mss_pm_ipc_msg_send()
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| /rk3399_ARM-atf/plat/amlogic/g12a/include/ |
| H A D | platform_def.h | 27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/amlogic/gxbb/include/ |
| H A D | platform_def.h | 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/imx/imx9/common/include/ |
| H A D | imx9_psci_common.h | 15 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
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| /rk3399_ARM-atf/plat/imx/imx8qm/include/ |
| H A D | platform_def.h | 27 #define IMX_PWR_LVL1 MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/qti/msm8916/ |
| H A D | msm8916_pm.c | 35 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
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| /rk3399_ARM-atf/plat/qti/qcs615/inc/ |
| H A D | platform_def.h | 30 #define QTI_PWR_LVL1 MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/qti/sc7180/inc/ |
| H A D | platform_def.h | 29 #define QTI_PWR_LVL1 MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/qti/kodiak/inc/ |
| H A D | kodiak_def.h | 30 #define QTI_PWR_LVL1 MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/brcm/board/stingray/src/ |
| H A D | pm.c | 66 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in brcm_pwr_domain_on_finish()
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| /rk3399_ARM-atf/plat/rpi/rpi4/include/ |
| H A D | platform_def.h | 29 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/rpi/rpi5/include/ |
| H A D | platform_def.h | 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/marvell/armada/a8k/common/include/ |
| H A D | platform_def.h | 178 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/include/plat/marvell/armada/a3k/common/ |
| H A D | marvell_def.h | 36 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/imx/imx8qx/ |
| H A D | imx8qx_psci.c | 127 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend()
203 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/imx/imx7/picopi/include/ |
| H A D | platform_def.h | 26 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/include/plat/marvell/armada/a8k/common/ |
| H A D | marvell_def.h | 33 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/imx/imx7/warp7/include/ |
| H A D | platform_def.h | 28 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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| /rk3399_ARM-atf/plat/marvell/armada/a3k/common/include/ |
| H A D | platform_def.h | 169 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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