Home
last modified time | relevance | path

Searched refs:reg (Results 1 – 25 of 126) sorted by relevance

123456

/optee_os/core/arch/arm/dts/
H A Dstm32mp23-st-scmi-cfg.dtsi20 reg = <1>;
26 reg = <0x14>;
33 reg = <CK_SCMI_ICN_HS_MCU>;
39 reg = <CK_SCMI_ICN_SDMMC>;
45 reg = <CK_SCMI_ICN_DDR>;
51 reg = <CK_SCMI_ICN_DISPLAY>;
57 reg = <CK_SCMI_ICN_HSL>;
63 reg = <CK_SCMI_ICN_NIC>;
69 reg = <CK_SCMI_ICN_VID>;
75 reg = <CK_SCMI_FLEXGEN_07>;
[all …]
H A Dstm32mp25-st-scmi-cfg.dtsi20 reg = <1>;
26 reg = <0x14>;
33 reg = <CK_SCMI_ICN_HS_MCU>;
39 reg = <CK_SCMI_ICN_SDMMC>;
45 reg = <CK_SCMI_ICN_DDR>;
51 reg = <CK_SCMI_ICN_DISPLAY>;
57 reg = <CK_SCMI_ICN_HSL>;
63 reg = <CK_SCMI_ICN_NIC>;
69 reg = <CK_SCMI_ICN_VID>;
75 reg = <CK_SCMI_FLEXGEN_07>;
[all …]
H A Dstm32mp21-st-scmi-cfg.dtsi20 reg = <1>;
26 reg = <0x14>;
33 reg = <CK_SCMI_ICN_HS_MCU>;
39 reg = <CK_SCMI_ICN_SDMMC>;
45 reg = <CK_SCMI_ICN_DDR>;
51 reg = <CK_SCMI_ICN_DISPLAY>;
57 reg = <CK_SCMI_ICN_HSL>;
63 reg = <CK_SCMI_ICN_NIC>;
69 reg = <CK_SCMI_FLEXGEN_07>;
75 reg = <CK_SCMI_FLEXGEN_08>;
[all …]
H A Dstm32mp257f-dk-ca35tdcid-resmem.dtsi14 reg = <0x0 0xa000000 0x0 0x20000>;
19 reg = <0x0 0xa020000 0x0 0x20000>;
24 reg = <0x0 0xa040000 0x0 0x1000>;
29 reg = <0x0 0xa041000 0x0 0x1000>;
34 reg = <0x0 0xa042000 0x0 0x1000>;
39 reg = <0x0 0xa043000 0x0 0x1d000>;
44 reg = <0x0 0xa060000 0x0 0x20000>;
49 reg = <0x0 0xa080000 0x0 0x1f000>;
54 reg = <0x0 0xa09f000 0x0 0x1000>;
60 reg = <0x0 0x10000000 0x0 0x10000000>;
[all …]
H A Dstm32mp257f-ev1-ca35tdcid-resmem.dtsi14 reg = <0x0 0xa000000 0x0 0x20000>;
19 reg = <0x0 0xa020000 0x0 0x20000>;
24 reg = <0x0 0xa040000 0x0 0x1000>;
29 reg = <0x0 0xa041000 0x0 0x1f000>;
34 reg = <0x0 0xa060000 0x0 0x20000>;
39 reg = <0x0 0xa080000 0x0 0x1f000>;
44 reg = <0x0 0xa09f000 0x0 0x1000>;
50 reg = <0x0 0x10000000 0x0 0x10000000>;
56 reg = <0x0 0x42000000 0x0 0x1000>;
61 reg = <0x0 0x42001000 0x0 0x1000>;
[all …]
H A Dstm32mp235f-dk-ca35tdcid-resmem.dtsi14 reg = <0x0 0xa000000 0x0 0x20000>;
19 reg = <0x0 0xa020000 0x0 0x20000>;
24 reg = <0x0 0xa040000 0x0 0x1000>;
29 reg = <0x0 0xa041000 0x0 0x1000>;
34 reg = <0x0 0xa042000 0x0 0x1000>;
39 reg = <0x0 0xa043000 0x0 0x1d000>;
44 reg = <0x0 0xa060000 0x0 0x20000>;
49 reg = <0x0 0xa080000 0x0 0x1f000>;
54 reg = <0x0 0xa09f000 0x0 0x1000>;
60 reg = <0x0 0x42000000 0x0 0x1000>;
[all …]
H A Dfsl-lx2160a-qds.dts41 reg = <0x00>;
47 reg = <0x8>;
53 reg = <0x18>;
59 reg = <0x19>;
65 reg = <0x1a>;
71 reg = <0x1b>;
77 reg = <0x1c>;
83 reg = <0x1d>;
89 reg = <0x1e>;
95 reg = <0x1f>;
[all …]
H A Dstm32mp131.dtsi25 reg = <0>;
71 reg = <0xa0021000 0x1000>,
140 reg = <0x4000f000 0x400>;
149 reg = <0x40010000 0x400>;
158 reg = <0x40011000 0x400>;
167 reg = <0x40012000 0x400>;
179 reg = <0x40013000 0x400>;
191 reg = <0x40018000 0x400>;
200 reg = <0x40019000 0x400>;
209 reg = <0x44003000 0x400>;
[all …]
H A Dfsl-lx2160a.dtsi31 reg = <0x0>;
48 reg = <0x1>;
65 reg = <0x100>;
82 reg = <0x101>;
99 reg = <0x200>;
116 reg = <0x201>;
133 reg = <0x300>;
150 reg = <0x301>;
167 reg = <0x400>;
184 reg = <0x401>;
[all …]
H A Dsama7g5.dtsi32 reg = <0x0>;
149 reg = <0>;
158 reg = <1>;
167 reg = <2>;
188 reg = <0x100000 0x3400>;
211 reg = <0x00200000 0x100000
223 reg = <0x00300000 0x100000
233 reg = <0x00400000 0x100000>;
241 reg = <0x00500000 0x100000>;
251 reg = <0x00600000 0x2400>;
[all …]
H A Dsama5d2.dtsi33 reg = <0>;
47 reg = <0x740000 0x1000>;
63 reg = <0x73c000 0x1000>;
79 reg = <0x20000000 0x20000000>;
98 reg = <0x00200000 0x20000>;
115 reg = <0x00100000 0x2400>;
124 reg = <0x00300000 0x100000
137 reg = <0x00400000 0x100000>;
149 reg = <0x00500000 0x100000>;
161 reg = <0x00a00000 0x1000>;
[all …]
H A Dstm32mp151.dtsi23 reg = <0>;
43 reg = <0xa0021000 0x1000>,
129 reg = <0x4c001000 0x400>;
143 reg = <0x50000000 0x1000>;
149 compatible = "st,stm32mp1-pwr-reg";
150 reg = <0x50001000 0x10>;
173 reg = <0x50001014 0x4>;
180 reg = <0x5000d000 0x400>;
260 reg = <0x50020000 0x400>;
266 reg = <0x50028000 0x100>;
[all …]
/optee_os/core/arch/arm/mm/
H A Dtee_pager.c284 struct vm_paged_region *reg) in pmem_is_covered_by_region() argument
286 if (pmem->fobj != reg->fobj) in pmem_is_covered_by_region()
288 if (pmem->fobj_pgidx < reg->fobj_pgoffs) in pmem_is_covered_by_region()
290 if ((pmem->fobj_pgidx - reg->fobj_pgoffs) >= in pmem_is_covered_by_region()
291 (reg->size >> SMALL_PAGE_SHIFT)) in pmem_is_covered_by_region()
305 static bool region_have_pgt(struct vm_paged_region *reg, struct pgt *pgt) in region_have_pgt() argument
309 for (n = 0; n < get_pgt_count(reg->base, reg->size); n++) in region_have_pgt()
310 if (reg->pgt_array[n] == pgt) in region_have_pgt()
317 struct vm_paged_region *reg) in pmem_get_region_tblidx() argument
319 size_t tbloffs = (reg->base & CORE_MMU_PGDIR_MASK) >> SMALL_PAGE_SHIFT; in pmem_get_region_tblidx()
[all …]
/optee_os/core/arch/arm/plat-telechips/drivers/
H A Dtcc_otp.c62 static void wait_for_ready(vaddr_t reg) in wait_for_ready() argument
64 while (!(io_read32(reg + GENERAL_STATUS) & STATUS_READY)) in wait_for_ready()
68 static void wait_for_done(vaddr_t reg) in wait_for_done() argument
70 while (!(io_read32(reg + OTP_CONTROL) & CTRL_DONE)) in wait_for_done()
76 vaddr_t reg = (vaddr_t)phys_to_virt_io(OTP_CMD_BASE, OTP_CMD_SIZE); in tcc_otp_read_128() local
81 offset < OTPROM_128_START || !buf || !reg) { in tcc_otp_read_128()
86 wait_for_ready(reg); in tcc_otp_read_128()
87 io_write32(reg + OTP_ADDRESS, offset); in tcc_otp_read_128()
88 io_write32(reg + OTP_CONTROL, CTRL_CMD_READ | CTRL_START); in tcc_otp_read_128()
89 wait_for_done(reg); in tcc_otp_read_128()
[all …]
/optee_os/core/drivers/qcom/ramblur/
H A Dramblur_pimem_v3.c58 static inline void readback_sync(uint32_t reg, uint32_t val, uint32_t mask, in readback_sync() argument
65 while (val != (in_dword_masked(reg, mask) >> shift)) in readback_sync()
72 uint32_t reg = RAMBLUR_WINn_CTL_ADDR(window); in enable() local
75 out_dword_masked_ns(reg, mask, val, RAMBLUR_WINn_CTL_INI(window)); in enable()
77 reg = RAMBLUR_WINn_STATUS_ADDR(window); in enable()
80 val = in_dword_masked(reg, mask) >> in enable()
88 uint32_t reg = RAMBLUR_WINn_CTL_ADDR(window); in disable_sw_init_mode() local
91 out_dword_masked_ns(reg, mask, val, RAMBLUR_WINn_CTL_INI(window)); in disable_sw_init_mode()
92 readback_sync(reg, val, mask, RAMBLUR_WINn_CTL_SW_INIT_MODE_SHFT); in disable_sw_init_mode()
98 uint32_t reg = RAMBLUR_WINn_CTL_ADDR(window); in disable() local
[all …]
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
H A Dhal_clk_mx6.c16 uint32_t reg = 0; in caam_hal_clk_enable() local
19 reg = io_read32(ccm_base + CCM_CCGR0); in caam_hal_clk_enable()
25 reg |= mask; in caam_hal_clk_enable()
27 reg &= ~mask; in caam_hal_clk_enable()
29 io_write32(ccm_base + CCM_CCGR0, reg); in caam_hal_clk_enable()
33 reg = io_read32(ccm_base + CCM_CCGR6); in caam_hal_clk_enable()
37 reg |= mask; in caam_hal_clk_enable()
39 reg &= ~mask; in caam_hal_clk_enable()
41 io_write32(ccm_base + CCM_CCGR6, reg); in caam_hal_clk_enable()
/optee_os/lib/libutils/ext/arch/riscv/
H A Dmcount_rv.S22 .macro get_pc reg argument
23 LDR \reg, REGOFF(3)(sp)
24 addi \reg, \reg, -4
28 .macro get_ra_addr reg argument
29 LDR \reg, REGOFF(2)(sp)
30 addi \reg, \reg, -4
36 .macro get_pc reg argument
37 LDR \reg, REGOFF(1)(sp)
38 addi \reg, \reg, -4
42 .macro get_ra_addr reg argument
[all …]
/optee_os/core/arch/arm/include/
H A Darm32_macros_cortex_a9.S31 .macro write_pcr reg argument
32 mcr p15, 0, \reg, c15, c0, 0
35 .macro read_pcr reg argument
36 mrc p15, 0, \reg, c15, c0, 0
39 .macro write_diag reg argument
40 mcr p15, 0, \reg, c15, c0, 1
43 .macro read_diag reg argument
44 mrc p15, 0, \reg, c15, c0, 1
H A Darm64_macros.S30 base_offs, reg argument
33 x\reg, [\base_reg, #\base_offs]
36 w\reg, [\base_reg, #\base_offs]
141 .macro adr_l reg, sym
142 adrp \reg, \sym
143 add \reg, \reg, :lo12:\sym
154 .macro read_apiakeylo reg argument
155 mrs \reg, S3_0_c2_c1_0
158 .macro read_apiakeyhi reg argument
159 mrs \reg, S3_0_c2_c1_1
[all …]
/optee_os/lib/libunw/
H A Dunwind_arm32.c176 static bool pop_vsp(uint32_t *reg, vaddr_t *vsp, vaddr_t stack, in pop_vsp() argument
181 if (*vsp + sizeof(*reg) > stack + stack_size) in pop_vsp()
184 if (!copy_in(reg, (void *)*vsp, sizeof(*reg))) in pop_vsp()
186 (*vsp) += sizeof(*reg); in pop_vsp()
210 unsigned int reg; in unwind_exec_insn() local
225 for (reg = 4; mask && reg < 16; mask >>= 1, reg++) { in unwind_exec_insn()
227 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
230 state->update_mask |= 1 << reg; in unwind_exec_insn()
233 if (reg == SP) in unwind_exec_insn()
246 unsigned int count, reg; in unwind_exec_insn() local
[all …]
/optee_os/core/arch/riscv/kernel/
H A Dcsr_detect.S12 .macro save_and_disable_xie reg argument
13 csrrw \reg, CSR_XIE, zero
16 .macro restore_xie reg argument
17 csrw CSR_XIE, \reg
20 .macro save_and_replace_xtvec reg, label
21 la \reg, \label
22 csrrw \reg, CSR_XTVEC, \reg
25 .macro restore_xtvec reg argument
26 csrw CSR_XTVEC, \reg
/optee_os/core/drivers/crypto/caam/
H A Dcaam_pwr.c62 const struct reglist *reg = NULL; in do_save_regs() local
68 reg = elem->regs; in do_save_regs()
70 for (idx = 0; idx < elem->nbentries; idx++, reg++) { in do_save_regs()
71 for (regidx = 0; regidx < reg->nbregs; in do_save_regs()
75 reg->offset + in do_save_regs()
77 elem->val[validx] &= ~reg->mask_clr; in do_save_regs()
80 elem->baseaddr + reg->offset + in do_save_regs()
92 const struct reglist *reg = NULL; in do_restore_regs() local
98 reg = elem->regs; in do_restore_regs()
100 for (idx = 0; idx < elem->nbentries; idx++, reg++) { in do_restore_regs()
[all …]
/optee_os/core/arch/arm/plat-rzn1/
H A Dsm_platform_handler.c38 vaddr_t reg = 0; in oem_sysreg() local
45 reg = core_mmu_get_va(addr, MEM_AREA_IO_SEC, sizeof(uint32_t)); in oem_sysreg()
50 if (!reg || !mask) in oem_sysreg()
52 PRIx32" (0x%"PRIxVA")", *pvalue, addr, reg); in oem_sysreg()
54 io_write32(reg, *pvalue); in oem_sysreg()
56 io_mask32(reg, *pvalue, mask); in oem_sysreg()
59 if (!reg || !auth->rmask) in oem_sysreg()
61 PRIxVA")", addr, reg); in oem_sysreg()
63 *pvalue = io_read32(reg) & auth->rmask; in oem_sysreg()
/optee_os/lib/libutils/ext/arch/arm/
H A Dmcount_a64.S19 .macro get_pc reg argument
20 ldr \reg, [x29, #8]
21 sub \reg, \reg, #4
25 .macro get_lr_addr reg argument
26 ldr \reg, [x29]
27 add \reg, \reg, #8
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dplat_tzc400.c82 struct tzc_region_config *reg; member
120 const struct tzc_region_config *reg) in tzc_region_check_overlap() argument
126 if (reg->base <= tzc_dev->reg[i].top && in tzc_region_check_overlap()
127 reg->top >= tzc_dev->reg[i].base) in tzc_region_check_overlap()
190 tzc_dev->reg[tzc_dev->nb_reg_used] = *region_cfg; in append_region()
201 struct tzc_region_non_sec *reg = NULL; in exclude_region_from_nsec() local
203 SLIST_FOREACH(reg, &nsec_region_list, link) { in exclude_region_from_nsec()
207 reg->region.base, in exclude_region_from_nsec()
208 reg->region.top + 1 - in exclude_region_from_nsec()
209 reg->region.base)) in exclude_region_from_nsec()
[all …]

123456