Home
last modified time | relevance | path

Searched refs:r1 (Results 1 – 25 of 46) sorted by relevance

12

/optee_os/core/arch/arm/kernel/
H A Dentry_a32.S44 mov r5, r1
57 mov r1, r5
68 ldr r1, =\line
95 ldr r1,=sem_cpu_sync
97 str r2, [r1, r0]
109 ldr r1, [r0]
110 cmp r1, r2
127 ldr r1, [r0]
128 cmp r1, r2
173 ubfx r1, r0, #MIDR_IMPLEMENTER_SHIFT, #MIDR_IMPLEMENTER_WIDTH
[all …]
H A Dtz_ssvce_pl310_a32.S23 add r1, r0, #PL310_DCACHE_LOCKDOWN_BASE
30 str r2, [r1], #PL310_LOCKDOWN_SZREG
31 str r2, [r1], #PL310_LOCKDOWN_SZREG
55 syncbyway_set_mask r1
56 str r1, [r0, #PL310_FLUSH_BY_WAY]
61 and r2, r2, r1
74 ldr r1, [r0, #PL310_SYNC]
75 cmp r1, #0
78 mov r1, #0
79 str r1, [r0, #PL310_SYNC]
[all …]
H A Dthread_a32.S31 mrs r1, cpsr
34 msr cpsr, r1
40 mrs r1, cpsr
43 msr cpsr, r1
49 mrs r1, cpsr
52 msr cpsr, r1
58 mrs r1, cpsr
61 msr cpsr, r1
66 mrs r1, cpsr
70 msr cpsr, r1
[all …]
H A Dspin_lock_a32.S42 ldrex r1, [r0]
43 cmp r1, #SPINLOCK_UNLOCK
45 strexeq r1, r2, [r0]
46 cmpeq r1, #0
55 mov r1, r0
57 ldrex r0, [r1]
60 strex r0, r2, [r1]
74 mov r1, #SPINLOCK_UNLOCK
75 str r1, [r0]
H A Dcache_helpers_a32.S35 add r1, r0, r1
41 cmp r0, r1
105 mov r1, #0
114 add r10, r1, r1, LSR #1 // Work out 3x current cache level
120 write_csselr r1 // select current cache level in csselr
133 orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
142 add r1, r1, #2 // increment the cache number
143 cmp r3, r1
195 sub r1, r3, #2
252 add r1, r0, r1
[all …]
H A Dmisc_a32.S41 ubfx r1, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
42 add r0, r0, r1, LSL #(CFG_CORE_CLUSTER_SHIFT)
49 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
51 add r1, r1, r2, LSL #(CFG_CORE_CLUSTER_SHIFT)
52 add r0, r0, r1, LSL #(CFG_CORE_THREAD_SHIFT)
63 mov r1, r0
64 cmp r1, #CPSR_MODE_USR /* update mode: usr -> sys */
65 moveq r1, #CPSR_MODE_SYS
69 orr r0, r1 /* set expected mode */
H A Dthread_optee_smc_a32.S50 mov r1, r0
63 pop {r1-r8}
87 mov r1, r0
98 mov r1, r0
109 mov r1, r0
120 mov r1, r0
131 mov r1, r0
142 mov r1, r0
187 mov r1, r4
213 mov r1, r4 /* CPSR to restore */
[all …]
H A Dvfp_a32.S15 read_cpacr r1
16 tst r1, #CPACR_D32DIS
25 read_cpacr r1
26 tst r1, #CPACR_D32DIS
H A Darch_scall_a32.S23 mov r9, r1
41 mov r1, r5
86 mov r1, #0 /* panic = false */
101 mov r1, #1 /* panic = true */
H A Darch_scall.c28 .r1 = pushed[2], in save_panic_regs_a32_ta()
58 (uaddr_t)regs->r1, TA32_CONTEXT_MAX_SIZE)) { in scall_save_panic_stack()
61 (uaddr_t)regs->r1); in scall_save_panic_stack()
65 save_panic_regs_a32_ta(tsd, (uint32_t *)regs->r1); in scall_save_panic_stack()
/optee_os/core/lib/libtomcrypt/src/ciphers/
H A Dserpent.c78 #define s_s0(i, r0, r1, r2, r3, r4) { \ argument
80 r4 = r1; \
81 r1 &= r3; \
83 r1 ^= r0; \
88 r2 |= r1; \
91 r4 |= r1; \
92 r1 ^= r3; \
93 r1 ^= r4; \
95 r1 ^= r3; \
99 #define s_i0(i, r0, r1, r2, r3, r4) { \ argument
[all …]
/optee_os/core/lib/libtomcrypt/src/stream/sosemanuk/
H A Dsosemanuk.c70 #define S0(r0, r1, r2, r3, r4) do { \ argument
71 r3 ^= r0; r4 = r1; \
72 r1 &= r3; r4 ^= r2; \
73 r1 ^= r0; r0 |= r3; \
75 r3 ^= r2; r2 |= r1; \
77 r4 |= r1; r1 ^= r3; \
78 r1 ^= r4; r3 |= r0; \
79 r1 ^= r3; r4 ^= r3; \
82 #define S1(r0, r1, r2, r3, r4) do { \ argument
84 r4 = r0; r0 &= r1; \
[all …]
/optee_os/lib/libutils/ext/arch/arm/
H A Datomic_a32.S12 ldrex r1, [r0]
13 add r1, r1, #1
14 strex r2, r1, [r0]
17 mov r0, r1
23 ldrex r1, [r0]
24 sub r1, r1, #1
25 strex r2, r1, [r0]
28 mov r0, r1
/optee_os/core/arch/arm/plat-hisilicon/
H A Dhi3519av100_plat_init.S40 mrrc p15, 1, r0, r1, c15
42 mcrr p15, 1, r0, r1, c15
47 mrs r1, cpsr
69 msr cpsr, r1
79 ldr r1, [r0]
80 orr r1, r1, #BIT(9) /* bit 9 set to 1 */
81 str r1, [r0]
/optee_os/core/arch/arm/sm/
H A Dsm_a32.S104 read_scr r1
105 tst r1, #SCR_NS
129 stmne r8, {r1-r4}
177 bic r1, r1, #(SCR_NS | SCR_FIQ) /* Clear NS and FIQ bit in SCR */
178 write_scr r1
224 read_scr r1
225 bic r1, r1, #(SCR_NS | SCR_FIQ) /* Clear NS and FIQ bit in SCR */
226 write_scr r1
333 mrs r1, cpsr
373 msr cpsr, r1
[all …]
H A Dpm_a32.S30 push {r0, r1}
32 mov r1, r5
100 ldr r1, [r0]
101 add r0, r0, r1
118 mov_imm r1, THREAD_CORE_LOCAL_SIZE
119 mla r0, r0, r1, r4
/optee_os/core/arch/arm/plat-ti/
H A Da9_plat_init.S61 ldr r1, =thread_core_local
62 ldr r1, [r1]
65 mla r3, r2, r0, r1
86 mov r1, #0
/optee_os/core/arch/arm/plat-stm/
H A Dtz_a9init.S30 mov r1, #0x1
31 str r1, [r0, #PL310_CTRL]
34 ldr r1, [r0, #PL310_AUX_CTRL]
35 tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */
/optee_os/core/pta/veraison_attestation/
H A Dhash.c33 const struct vm_region *r1 = *(const struct vm_region **)a; in cmp_regions() local
36 if (r1->size < r2->size) in cmp_regions()
39 if (r1->size > r2->size) in cmp_regions()
42 return memcmp((void *)r1->va, (void *)r2->va, r1->size); in cmp_regions()
/optee_os/lib/libmbedtls/mbedtls/library/
H A Dbn_mul.h1033 mbedtls_mpi_uint r0, r1;
1038 r1 = (mbedtls_mpi_uint)( r >> biL ); \
1039 r0 += c; r1 += (r0 < c); \
1040 r0 += *d; r1 += (r0 < *d); \
1041 c = r1; *(d++) = r0;
1051 mbedtls_mpi_uint r0, r1, rx, ry; \
1059 ry = s1 * b0; r1 = s1 * b1; \
1060 r1 += ( rx >> biH ); \
1061 r1 += ( ry >> biH ); \
1063 r0 += rx; r1 += (r0 < rx); \
[all …]
/optee_os/core/arch/arm/crypto/
H A Daes_modes_armv8a_ce_a32.S164 vld1.8 {q0-q1}, [r1]!
165 vld1.8 {q2}, [r1]!
174 vld1.8 {q0}, [r1]!
195 vld1.8 {q0-q1}, [r1]!
196 vld1.8 {q2}, [r1]!
205 vld1.8 {q0}, [r1]!
225 vld1.8 {q1}, [r1]! @ get next pt block
248 vld1.8 {q0-q1}, [r1]!
249 vld1.8 {q2}, [r1]!
266 vld1.8 {q0}, [r1]! @ get next ct block
[all …]
/optee_os/core/arch/arm/plat-vexpress/
H A Djuno_core_pos_a32.S13 and r1, r0, #MPIDR_CPU_MASK
16 add r0, r1, r0, LSR #6
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dreset.S21 mov_imm r1, STM32MP1_NSACR_PRESERVE_MASK
22 and r0, r0, r1
/optee_os/core/drivers/
H A Datmel_shdwc_a32.S48 ldr r6, [r1, #AT91_SHDW_CR]
73 str r4, [r1, #AT91_SHDW_CR]
/optee_os/core/arch/arm/include/
H A Darm64_macros.S95 .macro push, r1, r2
96 stp \r1, \r2, [sp, #-16]!
100 .macro pop, r1, r2
101 ldp \r1, \r2, [sp], #16

12