xref: /optee_os/core/arch/arm/plat-ti/a9_plat_init.S (revision e6c87b008df6d2b1496c01ae5d3b24df566e1285)
1/* SPDX-License-Identifier: BSD-2-Clause */
2/*
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
4 *	Andrew Davis <afd@ti.com>
5 */
6
7/*
8 * Entry points for the A9 init.
9 * It is assumed no stack is available when these routines are called.
10 * It is assumed each routine is called with return address in LR
11 * and with ARM registers R0, R1, R2, R3 being scratchable.
12 */
13
14#include <asm.S>
15#include <generated/asm-defines.h>
16#include <platform_config.h>
17#include <sm/optee_smc.h>
18#include <sm/teesmc_opteed.h>
19#include <sm/teesmc_opteed_macros.h>
20
21.arch_extension sec
22
23.section .text
24.balign 4
25.code 32
26
27booted:
28	.word	0
29
30/*
31 * Cortex A9 check for resume
32 *
33 * Use scratables registers R0-R3.
34 * No stack usage.
35 * LR store return address.
36 * Trap CPU in case of error.
37 */
38FUNC plat_cpu_reset_early , :
39	/* Check if we are resuming */
40	ldr	r3, =booted
41	ldr	r2, [r3]
42	cmp	r2, #0
43	/* Cold boot, mark our boot flag and return to normal boot */
44	moveq	r2, #1
45	streq	r2, [r3]
46	bxeq	lr
47	/* Otherwise we are resuming */
48	b	resume_springboard
49END_FUNC plat_cpu_reset_early
50
51LOCAL_FUNC resume_springboard , :
52UNWIND(	.cantunwind)
53	/* Setup tmp stack */
54	bl	__get_core_pos
55	cmp	r0, #CFG_TEE_CORE_NB_CORE
56	/* Unsupported CPU, park it before it breaks something */
57unhandled_cpu:
58	wfige
59	bge	unhandled_cpu
60
61	ldr	r1, =thread_core_local
62	ldr	r1, [r1]
63	mov	r2, #THREAD_CORE_LOCAL_SIZE
64	/* r3 = r2 * r0 + r1 */
65	mla	r3, r2, r0, r1
66	ldr	sp, [r3, #THREAD_CORE_LOCAL_TMP_STACK_VA_END]
67
68	/* Push our return on the stack as sm_pm_cpu_do_resume expects */
69	adr	lr, after_resume
70	push	{r4 - r12, lr}
71
72	/* Assumes suspend_regs is flat-mapped */
73	ldr	r0, =suspend_regs
74	bl	sm_pm_cpu_do_resume
75
76after_resume:
77	bl	thread_init_per_cpu
78
79	/* r5 contains the non-secure entry address (ARMv7 bootarg #0) */
80	mov	r0, r5
81	bl	init_sec_mon
82
83	bl	boot_primary_init_intc
84
85	mov	r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE
86	mov	r1, #0
87	mov	r2, #0
88	mov	r3, #0
89	mov	r4, #0
90	smc	#0
91	b	.	/* SMC should not return */
92END_FUNC resume_springboard
93