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/optee_os/core/
H A Dcrypto.mk102 CFG_CRYPTO_SHA3_ARM_CE ?= $(call cfg-one-enabled, CFG_CRYPTO_SHA3_224 \
244 _CFG_CORE_LTC_AES := $(call cfg-one-enabled, CFG_CRYPTO_XTS CFG_CRYPTO_CCM \
261 _CFG_CORE_LTC_MD5_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_MD5_DESC \
263 _CFG_CORE_LTC_SHA1_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA1_DESC \
265 _CFG_CORE_LTC_SHA224_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA224_DESC \
267 _CFG_CORE_LTC_SHA256_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA256_DESC \
270 _CFG_CORE_LTC_SHA384_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA384_DESC \
272 _CFG_CORE_LTC_SHA512_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA512_DESC \
275 _CFG_CORE_LTC_AES_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_AES_DESC \
278 _CFG_CORE_LTC_SHA3_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA3_224 \
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/optee_os/mk/
H A Dcheckconf.mk92 cfg-one-enabled = $(if $(filter y, $(foreach var,$(1),$($(var)))),y,n)
97 cfg-all-enabled = $(if $(strip $(1)),$(if $(call _cfg-all-enabled,$(1)),y,n),n)
98 _cfg-all-enabled = \
102 $(call _cfg-all-enabled,$(filter-out $(firstword $(1)),$(1))), \
115 $(if $(filter y,$(call cfg-all-enabled,$(2))), \
130 $(if $(filter y,$(call cfg-one-enabled,$(2))), \
H A Dconfig.mk66 # are enabled, panic and assert messages are more verbose, data and prefetch
93 # When this feature is enabled, calling mdbg_check(1) will print a list of all
151 # This is the default FS when enabled (i.e., the one used when
155 # CFG_REE_FS_HTREE_HASH_SIZE_COMPAT, when enabled, supports the legacy
188 # When enabled, the cache stores the first 'CFG_RPMB_FS_CACHE_ENTRIES' FAT FS
234 _CFG_WITH_SECURE_STORAGE := $(call cfg-one-enabled,CFG_REE_FS CFG_RPMB_FS)
274 # With CFG_TA_FLOAT_SUPPORT enabled TA code is free use floating point types
279 # If CFG_UNWIND is enabled, both the kernel and user mode call stacks can be
321 # When this flag is enabled, the ELF loader will introduce a random offset
335 # When this flag is enabled, th
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/optee_os/core/drivers/scmi-msg/
H A Dclock_generic.c27 bool enabled; member
140 return clk->enabled; in plat_scmi_clock_get_state()
158 if (!clk->enabled) { in plat_scmi_clock_set_state()
161 clk->enabled = true; in plat_scmi_clock_set_state()
164 if (clk->enabled) { in plat_scmi_clock_set_state()
166 clk->enabled = false; in plat_scmi_clock_set_state()
213 scmi_clk->enabled = false; in scmi_clk_add()
/optee_os/core/drivers/crypto/caam/
H A Dsub.mk13 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_HASH_DRV CFG_NXP_CAAM_HMAC_DRV) += hash
14 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_CIPHER_DRV CFG_NXP_CAAM_CMAC_DRV) += cipher
15 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_AE_CCM_DRV CFG_NXP_CAAM_AE_GCM_DRV) += ae
H A Dcrypto.mk184 ifeq ($(call cfg-one-enabled,CFG_NXP_CAAM_HMAC_DRV CFG_NXP_CAAM_CMAC_DRV),y)
194 ifeq ($(call cfg-one-enabled,CFG_NXP_CAAM_AE_CCM_DRV CFG_NXP_CAAM_AE_GCM_DRV),y)
224 ifeq ($(call cfg-one-enabled,CFG_CRYPTO_DRV_RSA CFG_CRYPTO_DRV_ECC \
/optee_os/core/drivers/crypto/se050/
H A Dcrypto.mk70 se050-one-enabled = $(call cfg-one-enabled, \
77 $(call force,CFG_NXP_SE05X_ACIPHER_DRV,$(call se050-one-enabled,RSA ECC))
97 $(call force,CFG_NXP_SE05X_CIPHER_DRV,$(call se050-one-enabled,CTR))
/optee_os/core/drivers/regulator/
H A Dregulator_fixed.c39 static TEE_Result fixed_set_state(struct regulator *regulator, bool enabled) in fixed_set_state() argument
44 if (enabled) { in fixed_set_state()
58 static TEE_Result fixed_get_state(struct regulator *regulator, bool *enabled) in fixed_get_state() argument
63 *enabled = gpio_get_value(regu->enable_gpio); in fixed_get_state()
65 *enabled = true; in fixed_get_state()
H A Dregulator_gpio.c43 bool enabled) in regulator_gpio_set_state() argument
48 if (enabled) { in regulator_gpio_set_state()
61 bool *enabled) in regulator_gpio_read_state() argument
66 *enabled = gpio_get_value(regu->enable_gpio); in regulator_gpio_read_state()
68 *enabled = true; in regulator_gpio_read_state()
/optee_os/core/include/dt-bindings/firewall/
H A Dstm32mp25-risab.h22 enabled, cid_read_list, cid_write_list, cid_priv_list) \ argument
26 ((enabled) << RISAB_CFEN_SHIFT) | \
H A Dstm32mp25-risaf.h36 sec, enc, enabled) \ argument
42 ((enabled) << DT_RISAF_EN_SHIFT) | \
/optee_os/core/tests/
H A Dnotif_test_wd.c18 bool enabled; member
65 if (!wd->enabled) { in wd_ndrv_atomic_cb()
70 wd->enabled = true; in wd_ndrv_atomic_cb()
/optee_os/lib/libmbedtls/core/
H A Dsub.mk4 srcs-$(call cfg-one-enabled, CFG_CRYPTO_MD5 CFG_CRYPTO_SHA1 CFG_CRYPTO_SHA224 \
25 srcs-$(call cfg-one-enabled, CFG_CRYPTO_RSA CFG_CRYPTO_DH \
/optee_os/core/drivers/
H A Datmel_wdt.c112 bool enabled; member
160 wdt->enabled = true; in atmel_wdt_enable()
174 wdt->enabled = false; in atmel_wdt_disable()
281 if (wdt->enabled) in atmel_wdt_pm()
285 if (wdt->enabled) in atmel_wdt_pm()
/optee_os/core/pta/
H A Dgprof.c101 sbuf->enabled = true; in gprof_start_pc_sampling()
127 if (sbuf->enabled) in gprof_stop_pc_sampling()
128 sbuf->enabled = false; in gprof_stop_pc_sampling()
H A Drtc.c45 pta_alarm->enabled = optee_alarm->enabled; in rtc_pta_copy_alarm_from_optee()
54 optee_alarm->enabled = pta_alarm->enabled; in rtc_pta_copy_alarm_to_optee()
/optee_os/core/drivers/imx/mu/
H A Dsub.mk2 srcs-$(call cfg-one-enabled,CFG_MX8ULP CFG_MX93 CFG_MX91 CFG_MX95 CFG_MX943) += imx_mu_8ulp_9x.c
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dconf.mk108 ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n)
109 $(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled)
111 ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y)
112 $(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled)
274 ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP \
425 ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID))
436 ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y)
H A Dscmi_server.c57 bool enabled; member
126 .enabled = (_init_enabled), \
135 .enabled = (_init_enabled), \
580 return (int32_t)clock->enabled; in plat_scmi_clock_get_state()
595 if (!clock->enabled) { in plat_scmi_clock_set_state()
598 clock->enabled = true; in plat_scmi_clock_set_state()
601 if (clock->enabled) { in plat_scmi_clock_set_state()
604 clock->enabled = false; in plat_scmi_clock_set_state()
1139 if (clk->enabled && in stm32mp1_init_scmi_server()
/optee_os/core/pta/tests/
H A Dsub.mk1 srcs-$(call cfg-all-enabled,CFG_REE_FS CFG_WITH_USER_TA) += fs_htree.c
/optee_os/core/lib/scmi-server/include/
H A Dscmi_agent_configuration.h25 bool enabled; member
/optee_os/lib/libutee/include/
H A Dpta_rtc.h53 uint8_t enabled; member
/optee_os/core/include/drivers/
H A Dregulator.h134 TEE_Result (*set_state)(struct regulator *r, bool enabled);
135 TEE_Result (*get_state)(struct regulator *r, bool *enabled);
/optee_os/ldelf/
H A Dsub.mk8 srcs-$(call cfg-one-enabled,CFG_RV32_$(sm) CFG_RV64_$(sm)) += syscalls_rv.S
/optee_os/core/drivers/crypto/stm32/
H A Dcrypto.mk13 ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y)

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