Searched refs:_reg (Results 1 – 5 of 5) sorted by relevance
| /optee_os/core/arch/arm/include/ |
| H A D | arm64_macros.S | 104 .macro mov_imm _reg, _val
106 movz \_reg, :abs_g1_s:\_val
109 movz \_reg, :abs_g2_s:\_val
111 movz \_reg, :abs_g3:\_val
112 movk \_reg, :abs_g2_nc:\_val
114 movk \_reg, :abs_g1_nc:\_val
116 movk \_reg, :abs_g0_nc:\_val
119 .macro add_imm _reg, _val
121 add \_reg, \_reg, ((\_val) >> 12), LSL #12
124 add \_reg, \_reg, ((\_val) & 0xfff)
[all …]
|
| /optee_os/core/drivers/clk/sam/ |
| H A D | at91_clk.h | 23 #define field_get(_mask, _reg) \ argument
27 (((_reg) & (__mask)) >> (ffs(__mask) - 1)); \
|
| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp25.c | 1006 #define CLK_PLL_CFG(_idx, _gate_id, _mux_id, _reg)\ argument
1010 .reg_pllxcfgr1 = (_reg),\
2588 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\ argument
2592 .pll_offset = (_reg),\
2602 #define STM32_PLL3(_name, _flags, _reg, _gate_id, _mux_id)\ argument
2606 .pll_offset = (_reg),\
2616 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\ argument
2620 .pll_offset = (_reg),\
|
| H A D | clk-stm32mp21.c | 988 #define CLK_PLL_CFG(_idx, _gate_id, _mux_id, _reg)\ argument
992 .reg_pllxcfgr1 = (_reg),\
2586 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\ argument
2590 .pll_offset = (_reg),\
2600 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\ argument
2604 .pll_offset = (_reg),\
|
| H A D | clk-stm32mp13.c | 907 #define CLK_PLL_CFG(_idx, _type, _gate_id, _mux_id, _reg)\ argument
912 .reg_pllxcr = (_reg),\
1968 #define STM32_PLL_VCO(_name, _nb_parents, _parents, _flags, _reg,\ argument
1973 .reg_pllxcr = (_reg),\
|