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Searched refs:UL (Results 1 – 25 of 40) sorted by relevance

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/optee_os/core/arch/arm/plat-automotive_rd/
H A Dplatform_config.h18 #define DRAM0_BASE UL(0x80000000)
26 #define UART1_BASE UL(0x1a410000)
28 #define CONSOLE_UART_CLK_IN_HZ UL(24000000)
31 #define GICD_BASE UL(0x20000000)
32 #define GICR_BASE UL(0x200C0000)
33 #define GICR_SIZE UL(0xF00000)
42 #define DRAM0_BASE UL(0x80000000)
48 #define SYS_COUNTER_FREQ_IN_TICKS UL(7372800)
52 #define UART0_BASE UL(0x2A400000)
53 #define UART1_BASE UL(0x2A410000)
[all …]
/optee_os/core/arch/arm/plat-qcom/
H A Dplatform_config.h16 #define DRAM0_BASE UL(0x80000000)
17 #define DRAM0_SIZE UL(0x80000000)
25 #define GENI_UART_REG_BASE UL(0x994000)
26 #define RAMBLUR_PIMEM_REG_BASE UL(0x610000)
27 #define SEC_PRNG_REG_BASE UL(0x010D1000)
30 #define GICD_BASE UL(0x17a00000)
31 #define GICR_BASE UL(0x17a60000)
/optee_os/lib/libutils/isoc/include/
H A Dstdint.h172 #define UL(v) v
178 #define UL(v) v ## UL macro
198 #define UINT64_C(v) UL(v)
201 #define UINTPTR_C(v) UL(v)
/optee_os/core/lib/libtomcrypt/src/pk/rsa/
H A Drsa_import.c30 LTC_ASN1_EOL, 0UL, NULL); in rsa_import_pkcs1()
39 LTC_ASN1_EOL, 0UL, NULL)) == CRYPT_OK) { in rsa_import_pkcs1()
60 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in rsa_import_pkcs1()
119 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in rsa_import()
H A Drsa_export.c50 LTC_ASN1_EOL, 0UL, NULL); in rsa_export()
74 LTC_ASN1_EOL, 0UL, NULL); in rsa_export()
H A Drsa_import_x509.c18 LTC_ASN1_EOL, 0UL, NULL); in s_rsa_decode()
H A Drsa_import_pkcs8.c86 LTC_SET_ASN1(alg_seq, 1, LTC_ASN1_NULL, NULL, 0UL); in rsa_import_pkcs8()
/optee_os/core/include/kernel/
H A Dtransfer_list.h25 #define TL_REG_CONVENTION_VER_SHIFT_64 UL(32)
26 #define TL_REG_CONVENTION_VER_SHIFT_32 UL(24)
27 #define TL_REG_CONVENTION_VER_MASK UL(0xff)
28 #define TL_REG_CONVENTION_VER UL(1)
/optee_os/core/lib/libtomcrypt/src/pk/dh/
H A Ddh_import.c33 LTC_ASN1_EOL, 0UL, NULL); in dh_import()
47 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in dh_import()
63 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in dh_import()
H A Ddh_export.c35 LTC_ASN1_EOL, 0UL, NULL); in dh_export()
46 LTC_ASN1_EOL, 0UL, NULL); in dh_export()
H A Ddh_set_pg_dhparam.c33 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in dh_set_pg_dhparam()
/optee_os/core/arch/arm/plat-corstone1000/
H A Dplatform_config.h47 #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */
49 #define CONSOLE_UART_CLK_IN_HZ UL(50000000) /* 50MHz*/
/optee_os/core/lib/libtomcrypt/src/pk/ecc/
H A Decc_import.c46 LTC_ASN1_EOL, 0UL, NULL); in ecc_import_ex()
67 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in ecc_import_ex()
78 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in ecc_import_ex()
H A Decc_export.c47 LTC_ASN1_EOL, 0UL, NULL); in ecc_export()
55 LTC_ASN1_EOL, 0UL, NULL); in ecc_export()
/optee_os/core/lib/libtomcrypt/src/pk/dsa/
H A Ddsa_import.c37 LTC_ASN1_EOL, 0UL, NULL); in dsa_import()
49 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in dsa_import()
63 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in dsa_import()
82 LTC_ASN1_EOL, 0UL, NULL) == CRYPT_OK) { in dsa_import()
H A Ddsa_export.c46 LTC_ASN1_EOL, 0UL, NULL); in dsa_export()
56 LTC_ASN1_EOL, 0UL, NULL); in dsa_export()
93 LTC_ASN1_EOL, 0UL, NULL); in dsa_export()
H A Ddsa_set_pqg_dsaparam.c35 LTC_ASN1_EOL, 0UL, NULL)) != CRYPT_OK) { in dsa_set_pqg_dsaparam()
/optee_os/core/lib/libtomcrypt/
H A Ded25519.c17 #define ED25519_KEY_SIZE UL(256)
92 if (*sig_len < UL(64)) { in crypto_acipher_ed25519_sign()
93 *sig_len = UL(64); in crypto_acipher_ed25519_sign()
128 if (*sig_len < UL(64)) { in crypto_acipher_ed25519ctx_sign()
129 *sig_len = UL(64); in crypto_acipher_ed25519ctx_sign()
H A Dx25519.c17 #define X25519_KEY_SIZE_BYTES UL(32)
/optee_os/core/arch/arm/plat-imx/
H A Dconf.mk423 CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
424 CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
447 CFG_DDR_SIZE ?= UL(0x180000000)
468 CFG_DDR_SIZE ?= UL(0x180000000)
478 CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
479 CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
492 CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
493 CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
510 CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
511 CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
[all …]
H A Dlink.mk8 $(q)ADDR=`printf 0x%x $$(($(subst UL,,$(CFG_TZDRAM_START))))`; \
/optee_os/core/lib/libtomcrypt/src/pk/asn1/x509/
H A Dx509_encode_subject_public_key_info.c61 LTC_ASN1_EOL, 0UL, NULL); in x509_encode_subject_public_key_info()
/optee_os/core/drivers/
H A Dmicrochip_pit.c12 #define MCHP_PIT64B_FREQ UL(5000000) /* 5 MHz */
/optee_os/core/arch/arm/plat-stm32mp2/
H A Dplatform_config.h87 #define DDR_BASE UL(0x80000000)
/optee_os/core/arch/arm/plat-rzn1/
H A Dsm_platform_handler.c53 else if (mask == ~0UL) in oem_sysreg()

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