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Searched refs:TEE_LOAD_ADDR (Results 1 – 24 of 24) sorted by relevance

/optee_os/core/arch/arm/plat-zynq7k/
H A Dplatform_config.h207 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR macro
209 #define TEE_LOAD_ADDR TEE_RAM_START macro
244 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR macro
246 #define TEE_LOAD_ADDR TEE_RAM_START macro
H A Dmain.c60 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); in plat_primary_init_early()
/optee_os/core/arch/arm/plat-versal/
H A Dplatform_config.h52 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR macro
54 #define TEE_LOAD_ADDR TEE_RAM_START macro
/optee_os/core/arch/arm/plat-sprd/
H A Dplatform_config.h70 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR macro
72 #define TEE_LOAD_ADDR TEE_RAM_START macro
/optee_os/core/arch/arm/plat-zynqmp/
H A Dplatform_config.h86 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR macro
88 #define TEE_LOAD_ADDR TEE_RAM_START macro
/optee_os/core/arch/arm/plat-ti/
H A Dplatform_config.h113 #define TEE_LOAD_ADDR (TEE_RAM_START + 0x1000) macro
130 #define TEE_LOAD_ADDR TEE_RAM_START macro
/optee_os/core/arch/arm/kernel/
H A Dkern.ld.S69 . = TEE_LOAD_ADDR;
70 ASSERT(!(TEE_LOAD_ADDR & (SMALL_PAGE_SIZE - 1)),
375 ASSERT(TEE_LOAD_ADDR >= TEE_RAM_START,
377 ASSERT(TEE_LOAD_ADDR < (TEE_RAM_START + TEE_RAM_PH_SIZE),
412 __init_size = __data_end - TEE_LOAD_ADDR;
H A Dboot.c324 asan_set_shadowed((void *)TEE_LOAD_ADDR, &__asan_shadow_start); in init_asan()
442 vaddr_t addr_end = (vaddr_t)__init_end - offs - TEE_LOAD_ADDR; in undo_init_relocation()
443 vaddr_t addr_start = (vaddr_t)__init_start - offs - TEE_LOAD_ADDR; in undo_init_relocation()
482 vaddr_t tzsram_end = TZSRAM_BASE + TZSRAM_SIZE - TEE_LOAD_ADDR + in init_pager_runtime()
H A Dentry_a64.S278 mov_imm x0, TEE_LOAD_ADDR /* Compiled load address */
H A Dentry_a32.S868 mov_imm r1, TEE_LOAD_ADDR
/optee_os/core/arch/riscv/kernel/
H A Dkern.ld.S73 . = TEE_LOAD_ADDR;
75 ASSERT(!(TEE_LOAD_ADDR & (SMALL_PAGE_SIZE - 1)),
237 __init_size = __data_end - TEE_LOAD_ADDR;
/optee_os/core/arch/arm/plat-poplar/
H A Dplatform_config.h147 #define TEE_LOAD_ADDR 0x03000000 /* BL32_BASE */ macro
/optee_os/core/arch/arm/include/mm/
H A Dgeneric_ram_layout.h114 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR macro
/optee_os/core/arch/riscv/include/mm/
H A Dgeneric_ram_layout.h115 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR macro
/optee_os/core/arch/arm/plat-rzn1/
H A Dpsci.c55 io_write32(sctl_va, TEE_LOAD_ADDR); in psci_cpu_on()
/optee_os/core/arch/arm/plat-hisilicon/
H A Dpsci.c83 val = virt_to_phys((void *)TEE_LOAD_ADDR); in psci_cpu_on()
/optee_os/core/drivers/pm/imx/
H A Dpsci.c59 imx_set_src_gpr_entry(core_idx, virt_to_phys((void *)TEE_LOAD_ADDR)); in psci_cpu_on()
/optee_os/core/arch/arm/plat-sunxi/
H A Dpsci.c89 val = virt_to_phys((void *)TEE_LOAD_ADDR); in psci_cpu_on()
/optee_os/core/arch/arm/plat-ls/
H A Dmain.c83 __compiler_bswap32(TEE_LOAD_ADDR)); in plat_primary_init_early()
/optee_os/core/include/mm/
H A Dcore_mmu.h49 #ifndef TEE_LOAD_ADDR
50 #define TEE_LOAD_ADDR TEE_RAM_START macro
/optee_os/core/arch/arm/plat-stm32mp1/pm/
H A Dpsci.c142 TEE_LOAD_ADDR); in release_secondary_early_hpen()
/optee_os/core/arch/arm/plat-vexpress/
H A Dmain.c278 mailbox->ep = TEE_LOAD_ADDR; in release_secondary_early_hpen()
/optee_os/core/arch/arm/plat-rockchip/
H A Dpsci_rk322x.c292 io_write32(isram_base + BOOT_ADDR_OFFSET, TEE_LOAD_ADDR); in psci_cpu_on()
/optee_os/core/mm/
H A Dcore_mmu.c50 const unsigned long core_mmu_tee_load_pa = TEE_LOAD_ADDR;
2599 if (pa >= TEE_LOAD_ADDR && pa < get_linear_map_end_pa()) { in phys_to_virt_tee_ram()