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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 6 of 6) sorted by relevance

/optee_os/core/include/drivers/
H A Dclk.h18 #define CLK_SET_RATE_PARENT BIT(3) /* propagate rate change up to parent */ macro
/optee_os/core/drivers/clk/
H A Dclk.c220 assert(!(clk->flags & CLK_SET_RATE_PARENT) || clk->parent); in clk_set_rate_no_lock()
221 if (clk->flags & CLK_SET_RATE_PARENT) { in clk_set_rate_no_lock()
H A Dclk-stm32mp13.c2075 .flags = CLK_SET_RATE_PARENT,
2090 .flags = CLK_SET_RATE_PARENT,
2141 .flags = CLK_SET_PARENT_PRE_ENABLE | CLK_SET_RATE_PARENT,
2153 .flags = CLK_SET_PARENT_PRE_ENABLE | CLK_SET_RATE_PARENT,
2165 .flags = CLK_SET_PARENT_PRE_ENABLE | CLK_SET_RATE_PARENT,
H A Dclk-stm32mp25.c2745 .flags = CLK_SET_RATE_PARENT,
2998 static STM32_GATE(ck_ker_stgen, &ck_flexgen_33, CLK_SET_RATE_PARENT,
3025 static STM32_GATE(ck_ker_ltdc, &ck_flexgen_27, CLK_SET_RATE_PARENT,
H A Dclk-stm32mp21.c2965 static STM32_GATE(ck_ker_stgen, &ck_flexgen_33, CLK_SET_RATE_PARENT,
2985 static STM32_GATE(ck_ker_ltdc, &ck_flexgen_27, CLK_SET_RATE_PARENT,
/optee_os/core/lib/scmi-server/
H A Dscmi_clock_consumer.c250 new_clock->flags = CLK_SET_RATE_PARENT; in optee_scmi_server_init_clocks()