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Searched refs:CA35SS_SSC_PLL_FREQ1_REFDIV_MASK (Results 1 – 3 of 3) sorted by relevance

/optee_os/core/arch/arm/plat-stm32mp2/
H A Dstm32_sysconf.h61 #define CA35SS_SSC_PLL_FREQ1_REFDIV_MASK GENMASK_32(21, 16) macro
64 #define CA35SS_SSC_PLL_FREQ1_MASK (CA35SS_SSC_PLL_FREQ1_REFDIV_MASK | \
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c2081 refdiv = (reg & CA35SS_SSC_PLL_FREQ1_REFDIV_MASK) >> in clk_get_pll1_fvco_rate()
H A Dclk-stm32mp25.c2074 refdiv = (reg & CA35SS_SSC_PLL_FREQ1_REFDIV_MASK) >> in clk_get_pll1_fvco_rate()