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Searched refs:sys_ctrl (Results 1 – 19 of 19) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/power/reset/
H A Doxnas-restart.c95 struct regmap *sys_ctrl; member
136 regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value); in ox820_restart_handle()
139 regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, in ox820_restart_handle()
161 regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value); in ox820_restart_handle()
166 regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0); in ox820_restart_handle()
167 regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0); in ox820_restart_handle()
168 regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0); in ox820_restart_handle()
169 regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0); in ox820_restart_handle()
170 regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0); in ox820_restart_handle()
171 regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0); in ox820_restart_handle()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhi6220.dtsi266 sys_ctrl: sys_ctrl@f7030000 { label
318 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
319 <&sys_ctrl HI6220_UART1_PCLK>;
332 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
333 <&sys_ctrl HI6220_UART2_PCLK>;
344 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
345 <&sys_ctrl HI6220_UART3_PCLK>;
356 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
357 <&sys_ctrl HI6220_UART4_PCLK>;
371 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
[all …]
H A Dhi6220-hikey.dts268 assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dhi6220.dtsi146 sys_ctrl: sys_ctrl@f7030000 { label
180 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
181 <&sys_ctrl HI6220_UART1_PCLK>;
191 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
192 <&sys_ctrl HI6220_UART2_PCLK>;
202 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
203 <&sys_ctrl HI6220_UART3_PCLK>;
212 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
213 <&sys_ctrl HI6220_UART4_PCLK>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dhisilicon,hi6220-reset.txt20 sys_ctrl: sys_ctrl@f7030000 {
33 resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/imx/dcss/
H A Ddcss-dpr.c104 u32 sys_ctrl; member
343 u32 sys_ctrl; in dcss_dpr_enable() local
345 sys_ctrl = (en ? REPEAT_EN | RUN_EN : 0); in dcss_dpr_enable()
353 if (ch->sys_ctrl != sys_ctrl) in dcss_dpr_enable()
356 ch->sys_ctrl = sys_ctrl; in dcss_dpr_enable()
539 ch->sys_ctrl, in dcss_dpr_write_sysctrl()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dhisilicon,hi6210-i2s.txt31 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
32 <&sys_ctrl HI6220_BBPPLL0_DIV>;
36 hisilicon,sysctrl-syscon = <&sys_ctrl>;
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_vop.c109 clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1)); in rkvop_enable_output()
113 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
118 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
123 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
128 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, in rkvop_enable_output()
H A Drk3288_vop.c78 setbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1)); in rk_vop_remove()
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Dstmfx.c118 u32 sys_ctrl; in stmfx_function_enable() local
122 ret = regmap_read(stmfx->map, STMFX_REG_SYS_CTRL, &sys_ctrl); in stmfx_function_enable()
133 (sys_ctrl & STMFX_REG_SYS_CTRL_ALTGPIO_EN)) { in stmfx_function_enable()
140 (sys_ctrl & STMFX_REG_SYS_CTRL_TS_EN)) { in stmfx_function_enable()
147 (sys_ctrl & STMFX_REG_SYS_CTRL_IDD_EN)) { in stmfx_function_enable()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dhi6220-clock.txt35 sys_ctrl: sys_ctrl@f7030000 {
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-hi6220-usb.txt15 hisilicon,peripheral-syscon = <&sys_ctrl>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dhisilicon-thermal.txt21 clocks = <&sys_ctrl HI6220_TSENSOR_CLK>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcoresight-cpu-debug.txt46 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
/OK3568_Linux_fs/kernel/drivers/video/rockchip/rga3/
H A Drga3_reg_info.c2054 uint32_t sys_ctrl; in rga3_set_reg() local
2083 sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(1); in rga3_set_reg()
2089 rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler); in rga3_set_reg()
2093 sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(0) | m_RGA3_SYS_CTRL_RGA_SART; in rga3_set_reg()
2098 rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler); in rga3_set_reg()
H A Drga2_reg_info.c2559 uint32_t sys_ctrl; in rga2_set_reg() local
2597 sys_ctrl = m_RGA2_SYS_CTRL_AUTO_CKG | m_RGA2_SYS_CTRL_AUTO_RST | in rga2_set_reg()
2603 sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(1); in rga2_set_reg()
2610 rga_write(sys_ctrl, RGA2_SYS_CTRL, scheduler); in rga2_set_reg()
2614 sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(0) | m_RGA2_SYS_CTRL_CMD_OP_ST_P; in rga2_set_reg()
2620 rga_write(sys_ctrl, RGA2_SYS_CTRL, scheduler); in rga2_set_reg()
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dimmap_5272.h34 typedef struct sys_ctrl { struct
H A Dimmap_5275.h64 typedef struct sys_ctrl { struct
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dvop_rk3288.h14 u32 sys_ctrl; member