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Searched refs:reset_mask (Results 1 – 25 of 36) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-usb.c84 u32 reset_mask; member
141 if (data->reset_mask == 0) in sunxi_usb_clk_setup()
159 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; in sunxi_usb_clk_setup()
167 .reset_mask = BIT(2) | BIT(1) | BIT(0),
180 .reset_mask = BIT(1) | BIT(0),
191 .reset_mask = BIT(2) | BIT(1) | BIT(0),
202 .reset_mask = BIT(2) | BIT(1) | BIT(0),
214 .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
225 .reset_mask = BIT(19) | BIT(18) | BIT(17),
239 .reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17),
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dni.c1748 u32 reset_mask = 0; in cayman_gpu_check_soft_reset() local
1759 reset_mask |= RADEON_RESET_GFX; in cayman_gpu_check_soft_reset()
1763 reset_mask |= RADEON_RESET_CP; in cayman_gpu_check_soft_reset()
1766 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in cayman_gpu_check_soft_reset()
1771 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()
1776 reset_mask |= RADEON_RESET_DMA1; in cayman_gpu_check_soft_reset()
1781 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()
1784 reset_mask |= RADEON_RESET_DMA1; in cayman_gpu_check_soft_reset()
1789 reset_mask |= RADEON_RESET_RLC; in cayman_gpu_check_soft_reset()
1792 reset_mask |= RADEON_RESET_IH; in cayman_gpu_check_soft_reset()
[all …]
H A Dr600.c1618 u32 reset_mask = 0; in r600_gpu_check_soft_reset() local
1629 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1636 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1641 reset_mask |= RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1644 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1649 reset_mask |= RADEON_RESET_DMA; in r600_gpu_check_soft_reset()
1654 reset_mask |= RADEON_RESET_RLC; in r600_gpu_check_soft_reset()
1657 reset_mask |= RADEON_RESET_IH; in r600_gpu_check_soft_reset()
1660 reset_mask |= RADEON_RESET_SEM; in r600_gpu_check_soft_reset()
1663 reset_mask |= RADEON_RESET_GRBM; in r600_gpu_check_soft_reset()
[all …]
H A Devergreen.c3828 u32 reset_mask = 0; in evergreen_gpu_check_soft_reset() local
3838 reset_mask |= RADEON_RESET_GFX; in evergreen_gpu_check_soft_reset()
3842 reset_mask |= RADEON_RESET_CP; in evergreen_gpu_check_soft_reset()
3845 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in evergreen_gpu_check_soft_reset()
3850 reset_mask |= RADEON_RESET_DMA; in evergreen_gpu_check_soft_reset()
3855 reset_mask |= RADEON_RESET_DMA; in evergreen_gpu_check_soft_reset()
3860 reset_mask |= RADEON_RESET_RLC; in evergreen_gpu_check_soft_reset()
3863 reset_mask |= RADEON_RESET_IH; in evergreen_gpu_check_soft_reset()
3866 reset_mask |= RADEON_RESET_SEM; in evergreen_gpu_check_soft_reset()
3869 reset_mask |= RADEON_RESET_GRBM; in evergreen_gpu_check_soft_reset()
[all …]
H A Dsi.c3776 u32 reset_mask = 0; in si_gpu_check_soft_reset() local
3787 reset_mask |= RADEON_RESET_GFX; in si_gpu_check_soft_reset()
3791 reset_mask |= RADEON_RESET_CP; in si_gpu_check_soft_reset()
3794 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in si_gpu_check_soft_reset()
3799 reset_mask |= RADEON_RESET_RLC; in si_gpu_check_soft_reset()
3804 reset_mask |= RADEON_RESET_DMA; in si_gpu_check_soft_reset()
3809 reset_mask |= RADEON_RESET_DMA1; in si_gpu_check_soft_reset()
3814 reset_mask |= RADEON_RESET_DMA; in si_gpu_check_soft_reset()
3817 reset_mask |= RADEON_RESET_DMA1; in si_gpu_check_soft_reset()
3823 reset_mask |= RADEON_RESET_IH; in si_gpu_check_soft_reset()
[all …]
H A Devergreen_dma.c173 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_dma_is_lockup() local
175 if (!(reset_mask & RADEON_RESET_DMA)) { in evergreen_dma_is_lockup()
H A Dcik.c4854 u32 reset_mask = 0; in cik_gpu_check_soft_reset() local
4865 reset_mask |= RADEON_RESET_GFX; in cik_gpu_check_soft_reset()
4868 reset_mask |= RADEON_RESET_CP; in cik_gpu_check_soft_reset()
4873 reset_mask |= RADEON_RESET_RLC; in cik_gpu_check_soft_reset()
4878 reset_mask |= RADEON_RESET_DMA; in cik_gpu_check_soft_reset()
4883 reset_mask |= RADEON_RESET_DMA1; in cik_gpu_check_soft_reset()
4888 reset_mask |= RADEON_RESET_DMA; in cik_gpu_check_soft_reset()
4891 reset_mask |= RADEON_RESET_DMA1; in cik_gpu_check_soft_reset()
4897 reset_mask |= RADEON_RESET_IH; in cik_gpu_check_soft_reset()
4900 reset_mask |= RADEON_RESET_SEM; in cik_gpu_check_soft_reset()
[all …]
H A Dsi_dma.c43 u32 reset_mask = si_gpu_check_soft_reset(rdev); in si_dma_is_lockup() local
51 if (!(reset_mask & mask)) { in si_dma_is_lockup()
H A Dni_dma.c289 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_dma_is_lockup() local
297 if (!(reset_mask & mask)) { in cayman_dma_is_lockup()
H A Dr600_dma.c210 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_dma_is_lockup() local
212 if (!(reset_mask & RADEON_RESET_DMA)) { in r600_dma_is_lockup()
H A Dcik_sdma.c777 u32 reset_mask = cik_gpu_check_soft_reset(rdev); in cik_sdma_is_lockup() local
785 if (!(reset_mask & mask)) { in cik_sdma_is_lockup()
/OK3568_Linux_fs/kernel/drivers/reset/
H A Dreset-ti-sci.c33 u32 reset_mask; member
91 reset_state |= control->reset_mask; in ti_sci_reset_set()
93 reset_state &= ~control->reset_mask; in ti_sci_reset_set()
169 return reset_state & control->reset_mask; in ti_sci_reset_status()
206 control->reset_mask = reset_spec->args[1]; in ti_sci_reset_of_xlate()
/OK3568_Linux_fs/u-boot/drivers/reset/
H A Dast2500-reset.c43 u32 reset_mode, reset_mask; in ast2500_reset_assert() local
52 reset_mask = ast_reset_mask_from_flags(reset_ctl->id); in ast2500_reset_assert()
54 (reset_mask & WDT_RESET_SDRAM); in ast2500_reset_assert()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dintel_gt_pm_irq.c62 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask) in gen6_gt_pm_reset_iir() argument
69 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
70 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
H A Dintel_gt_pm_irq.h20 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask);
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-twl6040.c33 const u8 reset_mask = TWL6040_HPLLRST; /* Same for HPPLL and LPPLL */ in twl6040_pdmclk_reset_one_clock() local
36 ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask); in twl6040_pdmclk_reset_one_clock()
40 ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask); in twl6040_pdmclk_reset_one_clock()
/OK3568_Linux_fs/u-boot/arch/arm/mach-aspeed/
H A Dast_wdt.c22 ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask) in ast_flags_from_reset_mode_mask() argument
27 ret |= (reset_mask << 2); in ast_flags_from_reset_mode_mask()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dwdt.h71 u32 reset_mask; member
102 ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
/OK3568_Linux_fs/kernel/drivers/misc/cxl/
H A Dhcalls.c439 u64 control_mask, u64 reset_mask) in cxl_h_control_faults() argument
448 control_mask, reset_mask); in cxl_h_control_faults()
450 unit_address, process_token, control_mask, reset_mask, in cxl_h_control_faults()
453 control_mask, reset_mask, retbuf[0], rc); in cxl_h_control_faults()
H A Dtrace.h610 u64 control_mask, u64 reset_mask, unsigned long r4,
614 control_mask, reset_mask, r4, rc),
620 __field(u64, reset_mask)
629 __entry->reset_mask = reset_mask;
639 __entry->reset_mask,
H A Dhcalls.h168 u64 control_mask, u64 reset_mask);
/OK3568_Linux_fs/kernel/drivers/net/ethernet/ibm/
H A Dibmveth.h73 unsigned long reset_mask, unsigned long set_mask, in h_illan_attributes() argument
80 reset_mask, set_mask); in h_illan_attributes()
/OK3568_Linux_fs/u-boot/drivers/watchdog/
H A Dast_wdt.c35 &priv->regs->reset_mask); in ast_wdt_start()
/OK3568_Linux_fs/kernel/sound/soc/tegra/
H A Dtegra210_i2s.c90 unsigned int reset_mask = I2S_SOFT_RESET_MASK; in tegra210_i2s_sw_reset() local
112 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en); in tegra210_i2s_sw_reset()
115 !(val & reset_mask & reset_en), in tegra210_i2s_sw_reset()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/smsc/
H A Dsmsc911x.c1440 unsigned int reset_mask = HW_CFG_SRST_; in smsc911x_soft_reset() local
1470 reset_mask = RESET_CTL_DIGITAL_RST_; in smsc911x_soft_reset()
1474 smsc911x_reg_write(pdata, reset_offset, reset_mask); in smsc911x_soft_reset()
1481 } while ((--timeout) && (temp & reset_mask)); in smsc911x_soft_reset()
1483 if (unlikely(temp & reset_mask)) { in smsc911x_soft_reset()

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