1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2017 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <wdt.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/wdt.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define WDT_AST2500 2500
15*4882a593Smuzhiyun #define WDT_AST2400 2400
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct ast_wdt_priv {
20*4882a593Smuzhiyun struct ast_wdt *regs;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
ast_wdt_start(struct udevice * dev,u64 timeout,ulong flags)23*4882a593Smuzhiyun static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct ast_wdt_priv *priv = dev_get_priv(dev);
26*4882a593Smuzhiyun ulong driver_data = dev_get_driver_data(dev);
27*4882a593Smuzhiyun u32 reset_mode = ast_reset_mode_from_flags(flags);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun clrsetbits_le32(&priv->regs->ctrl,
30*4882a593Smuzhiyun WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT,
31*4882a593Smuzhiyun reset_mode << WDT_CTRL_RESET_MODE_SHIFT);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC)
34*4882a593Smuzhiyun writel(ast_reset_mask_from_flags(flags),
35*4882a593Smuzhiyun &priv->regs->reset_mask);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun writel((u32) timeout, &priv->regs->counter_reload_val);
38*4882a593Smuzhiyun writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * Setting CLK1MHZ bit is just for compatibility with ast2400 part.
41*4882a593Smuzhiyun * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
42*4882a593Smuzhiyun * read-only
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun setbits_le32(&priv->regs->ctrl,
45*4882a593Smuzhiyun WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
ast_wdt_stop(struct udevice * dev)50*4882a593Smuzhiyun static int ast_wdt_stop(struct udevice *dev)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct ast_wdt_priv *priv = dev_get_priv(dev);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
ast_wdt_reset(struct udevice * dev)59*4882a593Smuzhiyun static int ast_wdt_reset(struct udevice *dev)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct ast_wdt_priv *priv = dev_get_priv(dev);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
ast_wdt_expire_now(struct udevice * dev,ulong flags)68*4882a593Smuzhiyun static int ast_wdt_expire_now(struct udevice *dev, ulong flags)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct ast_wdt_priv *priv = dev_get_priv(dev);
71*4882a593Smuzhiyun int ret;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun ret = ast_wdt_start(dev, 1, flags);
74*4882a593Smuzhiyun if (ret)
75*4882a593Smuzhiyun return ret;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun while (readl(&priv->regs->ctrl) & WDT_CTRL_EN)
78*4882a593Smuzhiyun ;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return ast_wdt_stop(dev);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
ast_wdt_ofdata_to_platdata(struct udevice * dev)83*4882a593Smuzhiyun static int ast_wdt_ofdata_to_platdata(struct udevice *dev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct ast_wdt_priv *priv = dev_get_priv(dev);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun priv->regs = devfdt_get_addr_ptr(dev);
88*4882a593Smuzhiyun if (IS_ERR(priv->regs))
89*4882a593Smuzhiyun return PTR_ERR(priv->regs);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const struct wdt_ops ast_wdt_ops = {
95*4882a593Smuzhiyun .start = ast_wdt_start,
96*4882a593Smuzhiyun .reset = ast_wdt_reset,
97*4882a593Smuzhiyun .stop = ast_wdt_stop,
98*4882a593Smuzhiyun .expire_now = ast_wdt_expire_now,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct udevice_id ast_wdt_ids[] = {
102*4882a593Smuzhiyun { .compatible = "aspeed,wdt", .data = WDT_AST2500 },
103*4882a593Smuzhiyun { .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 },
104*4882a593Smuzhiyun { .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 },
105*4882a593Smuzhiyun {}
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
ast_wdt_probe(struct udevice * dev)108*4882a593Smuzhiyun static int ast_wdt_probe(struct udevice *dev)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun debug("%s() wdt%u\n", __func__, dev->seq);
111*4882a593Smuzhiyun ast_wdt_stop(dev);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return 0;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun U_BOOT_DRIVER(ast_wdt) = {
117*4882a593Smuzhiyun .name = "ast_wdt",
118*4882a593Smuzhiyun .id = UCLASS_WDT,
119*4882a593Smuzhiyun .of_match = ast_wdt_ids,
120*4882a593Smuzhiyun .probe = ast_wdt_probe,
121*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct ast_wdt_priv),
122*4882a593Smuzhiyun .ofdata_to_platdata = ast_wdt_ofdata_to_platdata,
123*4882a593Smuzhiyun .ops = &ast_wdt_ops,
124*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
125*4882a593Smuzhiyun };
126