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Searched refs:pll_regs (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/mvebu/
H A Dap-cpu-clk.c141 const struct cpu_dfs_regs *pll_regs; member
151 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()
152 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_recalc_rate()
154 cpu_clkdiv_ratio &= clk->pll_regs->divider_mask; in ap_cpu_clk_recalc_rate()
155 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset; in ap_cpu_clk_recalc_rate()
167 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_set_rate()
168 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()
169 cpu_force_reg = clk->pll_regs->force_reg + in ap_cpu_clk_set_rate()
170 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()
171 cpu_ratio_reg = clk->pll_regs->ratio_reg + in ap_cpu_clk_set_rate()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c47 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m()
59 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk()
73 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk()
88 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk()
100 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk()
119 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1()
126 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2()
133 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3()
140 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4()
182 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in cpu_eth_init()
H A Dtimer.c92 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init()
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c108 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init() local
168 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
170 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
172 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
177 pll_regs + AR934X_PLL_CPU_CONFIG_REG); in ar934x_pll_init()
180 pll_regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_pll_init()
191 pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_pll_init()
198 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
200 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
202 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/lib/
H A Dasm-offsets.c81 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
82 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); in main()
83 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); in main()
84 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); in main()
85 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); in main()
86 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); in main()
87 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); in main()
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dadau17x1.c79 adau->pll_regs[5] = 1; in adau17x1_pll_event()
81 adau->pll_regs[5] = 0; in adau17x1_pll_event()
90 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); in adau17x1_pll_event()
358 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs); in adau17x1_set_dai_pll()
364 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); in adau17x1_set_dai_pll()
1057 adau->pll_regs); in adau17x1_probe()
H A Dadau1373.c1257 uint8_t pll_regs[5]; in adau1373_set_pll() local
1299 ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs); in adau1373_set_pll()
1315 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]); in adau1373_set_pll()
1316 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]); in adau1373_set_pll()
1317 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]); in adau1373_set_pll()
1318 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]); in adau1373_set_pll()
1319 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]); in adau1373_set_pll()
H A Dadau17x1.h45 uint8_t pll_regs[6]; member
/OK3568_Linux_fs/u-boot/board/armadeus/apf27/
H A Dfpga.c194 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in apf27_fpga_setup()
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun50i-h6.c1160 static const u32 pll_regs[] = { variable
1197 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun50i_h6_ccu_probe()
1198 val = readl(reg + pll_regs[i]); in sun50i_h6_ccu_probe()
1200 writel(val, reg + pll_regs[i]); in sun50i_h6_ccu_probe()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h115 struct pll_regs { struct
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dov2659.c936 struct sensor_register pll_regs[] = { in ov2659_set_pixel_clock() local
945 return ov2659_write_array(client, pll_regs); in ov2659_set_pixel_clock()
/OK3568_Linux_fs/kernel/drivers/video/fbdev/aty/
H A Datyfb_base.c3067 u8 pll_regs[16]; in atyfb_setup_sparc() local
3090 pll_regs[i] = aty_ld_pll_ct(i, par); in atyfb_setup_sparc()
3095 M = pll_regs[PLL_REF_DIV]; in atyfb_setup_sparc()
3100 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; in atyfb_setup_sparc()
3105 P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) | in atyfb_setup_sparc()
3106 ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)]; in atyfb_setup_sparc()