1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is used to generate definitions needed by
5*4882a593Smuzhiyun * assembly language modules.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * We use the technique used in the OSF Mach kernel code:
8*4882a593Smuzhiyun * generate asm statements containing #defines,
9*4882a593Smuzhiyun * compile this file to assembler, and then extract the
10*4882a593Smuzhiyun * #defines from the assembly-language output.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <linux/kbuild.h>
17*4882a593Smuzhiyun #include <linux/arm-smccc.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
20*4882a593Smuzhiyun || defined(CONFIG_MX51) || defined(CONFIG_MX53)
21*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
22*4882a593Smuzhiyun #endif
23*4882a593Smuzhiyun
main(void)24*4882a593Smuzhiyun int main(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * TODO : Check if each entry in this file is really necessary.
28*4882a593Smuzhiyun * - struct esdramc_regs
29*4882a593Smuzhiyun * - struct max_regs
30*4882a593Smuzhiyun * - struct aips_regs
31*4882a593Smuzhiyun * - struct aipi_regs
32*4882a593Smuzhiyun * - struct clkctl
33*4882a593Smuzhiyun * - struct dpll
34*4882a593Smuzhiyun * are used only for generating asm-offsets.h.
35*4882a593Smuzhiyun * It means their offset addresses are referenced only from assembly
36*4882a593Smuzhiyun * code. Is it better to define the macros directly in headers?
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #if defined(CONFIG_MX25)
40*4882a593Smuzhiyun /* Clock Control Module */
41*4882a593Smuzhiyun DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
42*4882a593Smuzhiyun DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
43*4882a593Smuzhiyun DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
44*4882a593Smuzhiyun DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
45*4882a593Smuzhiyun DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
46*4882a593Smuzhiyun DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Enhanced SDRAM Controller */
49*4882a593Smuzhiyun DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
50*4882a593Smuzhiyun DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
51*4882a593Smuzhiyun DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Multi-Layer AHB Crossbar Switch */
54*4882a593Smuzhiyun DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
55*4882a593Smuzhiyun DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
56*4882a593Smuzhiyun DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
57*4882a593Smuzhiyun DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
58*4882a593Smuzhiyun DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
59*4882a593Smuzhiyun DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
60*4882a593Smuzhiyun DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
61*4882a593Smuzhiyun DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
62*4882a593Smuzhiyun DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
63*4882a593Smuzhiyun DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
64*4882a593Smuzhiyun DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
65*4882a593Smuzhiyun DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
66*4882a593Smuzhiyun DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
67*4882a593Smuzhiyun DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
68*4882a593Smuzhiyun DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* AHB <-> IP-Bus Interface */
71*4882a593Smuzhiyun DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
72*4882a593Smuzhiyun DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #if defined(CONFIG_MX27)
76*4882a593Smuzhiyun DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
77*4882a593Smuzhiyun DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
78*4882a593Smuzhiyun DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
79*4882a593Smuzhiyun DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
82*4882a593Smuzhiyun DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
83*4882a593Smuzhiyun DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
84*4882a593Smuzhiyun DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
85*4882a593Smuzhiyun DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
86*4882a593Smuzhiyun DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
87*4882a593Smuzhiyun DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
90*4882a593Smuzhiyun DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
91*4882a593Smuzhiyun DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
92*4882a593Smuzhiyun DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
93*4882a593Smuzhiyun DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
96*4882a593Smuzhiyun offsetof(struct system_control_regs, gpcr));
97*4882a593Smuzhiyun DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
98*4882a593Smuzhiyun offsetof(struct system_control_regs, fmcr));
99*4882a593Smuzhiyun #endif
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #if defined(CONFIG_MX35)
102*4882a593Smuzhiyun /* Round up to make sure size gives nice stack alignment */
103*4882a593Smuzhiyun DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
104*4882a593Smuzhiyun DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
105*4882a593Smuzhiyun DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
106*4882a593Smuzhiyun DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
107*4882a593Smuzhiyun DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
108*4882a593Smuzhiyun DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
109*4882a593Smuzhiyun DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
110*4882a593Smuzhiyun DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
111*4882a593Smuzhiyun DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
112*4882a593Smuzhiyun DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
113*4882a593Smuzhiyun DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
114*4882a593Smuzhiyun DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
115*4882a593Smuzhiyun DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
116*4882a593Smuzhiyun DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
117*4882a593Smuzhiyun DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* Multi-Layer AHB Crossbar Switch */
120*4882a593Smuzhiyun DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
121*4882a593Smuzhiyun DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
122*4882a593Smuzhiyun DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
123*4882a593Smuzhiyun DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
124*4882a593Smuzhiyun DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
125*4882a593Smuzhiyun DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
126*4882a593Smuzhiyun DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
127*4882a593Smuzhiyun DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
128*4882a593Smuzhiyun DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
129*4882a593Smuzhiyun DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
130*4882a593Smuzhiyun DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
131*4882a593Smuzhiyun DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
132*4882a593Smuzhiyun DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
133*4882a593Smuzhiyun DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
134*4882a593Smuzhiyun DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
135*4882a593Smuzhiyun DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* AHB <-> IP-Bus Interface */
138*4882a593Smuzhiyun DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
139*4882a593Smuzhiyun DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
140*4882a593Smuzhiyun DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
141*4882a593Smuzhiyun DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
142*4882a593Smuzhiyun DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
143*4882a593Smuzhiyun DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
144*4882a593Smuzhiyun DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
145*4882a593Smuzhiyun DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
146*4882a593Smuzhiyun DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
147*4882a593Smuzhiyun DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
148*4882a593Smuzhiyun DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
149*4882a593Smuzhiyun #endif
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
152*4882a593Smuzhiyun /* Round up to make sure size gives nice stack alignment */
153*4882a593Smuzhiyun DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
154*4882a593Smuzhiyun DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
155*4882a593Smuzhiyun DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
156*4882a593Smuzhiyun DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
157*4882a593Smuzhiyun DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
158*4882a593Smuzhiyun DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
159*4882a593Smuzhiyun DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
160*4882a593Smuzhiyun DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
161*4882a593Smuzhiyun DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
162*4882a593Smuzhiyun DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
163*4882a593Smuzhiyun DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
164*4882a593Smuzhiyun DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
165*4882a593Smuzhiyun DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
166*4882a593Smuzhiyun DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
167*4882a593Smuzhiyun DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
168*4882a593Smuzhiyun DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
169*4882a593Smuzhiyun DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
170*4882a593Smuzhiyun DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
171*4882a593Smuzhiyun DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
172*4882a593Smuzhiyun DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
173*4882a593Smuzhiyun DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
174*4882a593Smuzhiyun DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
175*4882a593Smuzhiyun DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
176*4882a593Smuzhiyun DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
177*4882a593Smuzhiyun DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
178*4882a593Smuzhiyun DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
179*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
180*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
181*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
182*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
183*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
184*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
185*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
186*4882a593Smuzhiyun DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
187*4882a593Smuzhiyun #if defined(CONFIG_MX53)
188*4882a593Smuzhiyun DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
189*4882a593Smuzhiyun #endif
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* DPLL */
192*4882a593Smuzhiyun DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
193*4882a593Smuzhiyun DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
194*4882a593Smuzhiyun DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
195*4882a593Smuzhiyun DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
196*4882a593Smuzhiyun DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
197*4882a593Smuzhiyun DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
198*4882a593Smuzhiyun DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
199*4882a593Smuzhiyun DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
200*4882a593Smuzhiyun #endif
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun #ifdef CONFIG_ARM_SMCCC
203*4882a593Smuzhiyun DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
204*4882a593Smuzhiyun DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
205*4882a593Smuzhiyun DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
206*4882a593Smuzhiyun DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
207*4882a593Smuzhiyun #endif
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun return 0;
210*4882a593Smuzhiyun }
211