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Searched refs:SDMA0_REGISTER_OFFSET (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dcik_sdma.c72 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_rptr()
96 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_wptr()
117 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_set_wptr()
261 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
311 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
343 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_enable()
376 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_resume()
484 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()
486 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); in cik_sdma_load_microcode()
487 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()
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H A Dcik.c174 case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET): in cik_get_allowed_info_register()
3337 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
4822 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
4876 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
4964 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
4966 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5167 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5169 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5522 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5523 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
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H A Dcikd.h1952 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dcik_sdma.c49 SDMA0_REGISTER_OFFSET,
887 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
890 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
893 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
908 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
911 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
918 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
921 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
1077 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_soft_reset()
1079 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
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H A Dsdma_v2_4.c62 SDMA0_REGISTER_OFFSET,
971 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
973 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
1015 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1017 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1020 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1022 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
H A Dsdma_v3_0.c76 SDMA0_REGISTER_OFFSET,
1349 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1351 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1354 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1356 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
H A Dvid.h26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
H A Dcikd.h484 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
H A Dvi.c461 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
H A Dcik.c976 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},