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Searched refs:REG_FPGA0_IQK (Results 1 – 25 of 41) sorted by relevance

12

/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8723b.c569 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
571 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
606 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
609 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
642 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
644 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
679 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
681 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
716 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
719 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
[all …]
H A Drtl8xxxu_8192e.c735 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_a()
737 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_a()
776 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
789 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
824 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
834 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
846 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
872 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
892 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
894 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/halrf/rtl8723b/
H A Dhalrf_8723b_win.c623 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_iqk_8723b()
632 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_iqk_8723b()
654 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_iqk_8723b()
719 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8723b()
733 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk_8723b()
752 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8723b()
809 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8723b()
821 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk_8723b()
842 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8723b()
906 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_b_iqk_8723b()
[all …]
H A Dhalrf_8723b_ap.c567 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8723b()
597 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_iqk_8723b()
622 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8723b()
659 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
670 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8723b()
692 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8723b()
717 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
747 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
779 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8723b()
804 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
[all …]
H A Dhalrf_8723b_ce.c587 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8723b()
619 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_iqk_8723b()
648 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8723b()
693 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
705 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8723b()
728 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8723b()
757 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
787 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
820 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8723b()
849 odm_set_bb_reg(p_dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8723b()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/hal/phydm/halrf/rtl8188f/
H A Dhalrf_8188f.c745 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
755 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_iqk_8188f()
780 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
819 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
829 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
856 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
887 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
897 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
923 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
974 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/hal/phydm/halrf/rtl8188f/
H A Dhalrf_8188f.c745 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
755 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_iqk_8188f()
780 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
819 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
829 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
856 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
887 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
897 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
923 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
974 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/hal/phydm/halrf/rtl8188f/
H A Dhalrf_8188f.c744 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
754 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_iqk_8188f()
779 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
818 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
828 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
855 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
886 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
896 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
922 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
973 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/hal/phydm/halrf/rtl8188f/
H A Dhalrf_8188f.c744 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
754 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_iqk_8188f()
779 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_iqk_8188f()
818 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
828 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
855 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
886 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
896 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk_8188f()
922 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk_8188f()
973 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/phydm/halrf/rtl8188e/
H A Dhalrf_8188e_win.c601 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_iqk_8188e()
611 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_iqk_8188e()
633 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_iqk_8188e()
682 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk()
692 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk()
719 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk()
745 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk()
755 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk()
781 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk()
1097 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in _phy_path_a_stand_by()
[all …]
H A Dhalrf_8188e_ap.c328 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0); in phy_path_a_rx_iqk()
333 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk()
382 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0); in phy_path_a_rx_iqk()
387 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk()
716 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x0); in _phy_path_a_stand_by()
718 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in _phy_path_a_stand_by()
897 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in _phy_iq_calibrate_8188e()
964 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0); in _phy_iq_calibrate_8188e()
H A Dhalrf_8188e_ce.c643 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk()
648 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk()
698 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000); in phy_path_a_rx_iqk()
703 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in phy_path_a_rx_iqk()
993 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x0); in _phy_path_a_stand_by()
995 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in _phy_path_a_stand_by()
1152 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); in _phy_iq_calibrate_8188e()
1221 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0); in _phy_iq_calibrate_8188e()
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/halrf/rtl8703b/
H A Dhalrf_8703b.c611 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_iqk_8703b()
619 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_iqk_8703b()
662 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_iqk_8703b()
719 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8703b()
729 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk_8703b()
772 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8703b()
827 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8703b()
839 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); in phy_path_a_rx_iqk_8703b()
882 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in phy_path_a_rx_iqk_8703b()
1528 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); in _phy_iq_calibrate_8703b()
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/include/
H A Dhal_phy_reg.h98 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/
H A Dhal_phy_reg.h98 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/
H A Dhal_phy_reg.h99 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/include/
H A Dhal_phy_reg.h99 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/include/
H A Dhal_phy_reg.h98 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/include/
H A Dhal_phy_reg.h99 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/include/
H A Dhal_phy_reg.h98 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/include/
H A Dhal_phy_reg.h98 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/include/
H A Dhal_phy_reg.h98 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/include/
H A Dhal_phy_reg.h98 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/include/
H A Dhal_phy_reg.h99 #define REG_FPGA0_IQK rFPGA0_IQK macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/include/
H A Dhal_phy_reg.h99 #define REG_FPGA0_IQK rFPGA0_IQK macro

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