1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
18 #if (DM_ODM_SUPPORT_TYPE == 0x08) /*[PHYDM-262] workaround for SD4 compile warning*/
19 #if RT_PLATFORM == PLATFORM_MACOSX
20 #include "phydm_precomp.h"
21 #else
22 #include "../phydm_precomp.h"
23 #endif
24 #else
25 #include "../../phydm_precomp.h"
26 #endif
27
28 #if (RTL8188F_SUPPORT == 1)
29
30 #define MASKH3BYTES 0xffffff00
31
32 /* #define SUCCESS 0 */
33 /* #define FAIL -1 */
34
35 /*---------------------------Define Local Constant---------------------------*/
36 /* 2010/04/25 MH Define the max tx power tracking tx agc power. */
37 #define ODM_TXPWRTRACK_MAX_IDX8188F 6
38
39 /* MACRO definition for cali_info->TxIQC_8188F[0] */
40 #define PATH_S0 1 /* RF_PATH_B */
41 #define idx_0xc94 0
42 #define idx_0xc80 1
43 #define idx_0xc4c 2
44 #define idx_0xc14 0
45 #define idx_0xca0 1
46 #define KEY 0
47 #define VAL 1
48
49 /* MACRO definition for cali_info->TxIQC_8188F[1] */
50 #define PATH_S1 0 /* RF_PATH_A */
51 #define idx_0xc9c 0
52 #define idx_0xc88 1
53 #define idx_0xc4c 2
54 #define idx_0xc1c 0
55 #define idx_0xc78 1
56
57 /*---------------------------Define Local Constant---------------------------*/
58
59 /* 3============================================================
60 * 3 Tx Power Tracking
61 * 3============================================================ */
62
set_iqk_matrix_8188f(struct dm_struct * dm,s8 OFDM_index,u8 rf_path,s32 iqk_result_x,s32 iqk_result_y)63 void set_iqk_matrix_8188f(struct dm_struct *dm, s8 OFDM_index, u8 rf_path,
64 s32 iqk_result_x, s32 iqk_result_y)
65 {
66 s32 ele_A = 0, ele_D, ele_C = 0, value32;
67
68 if (OFDM_index >= OFDM_TABLE_SIZE)
69 OFDM_index = OFDM_TABLE_SIZE - 1;
70 else if (OFDM_index < 0)
71 OFDM_index = 0;
72
73 ele_D = (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22;
74
75 /* new element A = element D x X */
76 if (iqk_result_x != 0 && (*dm->band_type == ODM_BAND_2_4G)) {
77 if ((iqk_result_x & 0x00000200) != 0) /* consider minus */
78 iqk_result_x = iqk_result_x | 0xFFFFFC00;
79 ele_A = ((iqk_result_x * ele_D) >> 8) & 0x000003FF;
80
81 /* new element C = element D x Y */
82 if ((iqk_result_y & 0x00000200) != 0)
83 iqk_result_y = iqk_result_y | 0xFFFFFC00;
84 ele_C = ((iqk_result_y * ele_D) >> 8) & 0x000003FF;
85
86 if (rf_path == RF_PATH_A)
87 switch (rf_path) {
88 case RF_PATH_A:
89 /* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
90 value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
91 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
92
93 value32 = (ele_C & 0x000003C0) >> 6;
94 odm_set_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
95
96 value32 = ((iqk_result_x * ele_D) >> 7) & 0x01;
97 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32);
98 break;
99 case RF_PATH_B:
100 /* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
101 value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
102 odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
103
104 value32 = (ele_C & 0x000003C0) >> 6;
105 odm_set_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
106
107 value32 = ((iqk_result_x * ele_D) >> 7) & 0x01;
108 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32);
109
110 break;
111 default:
112 break;
113 }
114 } else {
115 switch (rf_path) {
116 case RF_PATH_A:
117 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
118 odm_set_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
119 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00);
120 break;
121
122 case RF_PATH_B:
123 odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
124 odm_set_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
125 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00);
126 break;
127
128 default:
129 break;
130 }
131 }
132
133 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
134 "TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
135 (u32)iqk_result_x, (u32)iqk_result_y, (u32)ele_A, (u32)ele_C,
136 (u32)ele_D, (u32)iqk_result_x, (u32)iqk_result_y);
137 }
138
do_iqk_8188f(void * dm_void,u8 delta_thermal_index,u8 thermal_value,u8 threshold)139 void do_iqk_8188f(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
140 u8 threshold)
141 {
142 struct dm_struct *dm = (struct dm_struct *)dm_void;
143
144 odm_reset_iqk_result(dm);
145 dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
146 halrf_iqk_trigger(dm, false);
147 }
148
149 /*-----------------------------------------------------------------------------
150 * Function: odm_TxPwrTrackSetPwr88E()
151 *
152 * Overview: 88E change all channel tx power accordign to flag.
153 * OFDM & CCK are all different.
154 *
155 * Input: NONE
156 *
157 * Output: NONE
158 *
159 * Return: NONE
160 *
161 * Revised History:
162 * When Who Remark
163 * 04/23/2012 MHC Create version 0.
164 *
165 *---------------------------------------------------------------------------*/
odm_tx_pwr_track_set_pwr_8188f(void * dm_void,enum pwrtrack_method method,u8 rf_path,u8 channel_mapped_index)166 void odm_tx_pwr_track_set_pwr_8188f(void *dm_void, enum pwrtrack_method method,
167 u8 rf_path, u8 channel_mapped_index)
168 {
169 struct dm_struct *dm = (struct dm_struct *)dm_void;
170 void *adapter = dm->adapter;
171 //PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
172 u8 pwr_tracking_limit_ofdm = 32;
173 u8 pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1; /* -2dB */
174 u8 tx_rate = 0xFF;
175 s8 final_ofdm_swing_index = 0;
176 s8 final_cck_swing_index = 0;
177 /* u8 i = 0; */
178 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
179
180 #if 0
181 struct _hal_rf_ *rf = &(dm->rf_table);
182
183 if (*dm->mp_mode == true) {
184 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
185 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
186 #if (MP_DRIVER == 1)
187 PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
188
189 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
190 #endif
191 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
192 #ifdef CONFIG_MP_INCLUDED
193 PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
194
195 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
196 #endif
197 #endif
198 #endif
199 } else {
200 u16 rate = *(dm->forced_data_rate);
201
202 if (!rate) { /*auto rate*/
203 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
204 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
205 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
206 if (dm->number_linked_client != 0)
207 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
208 else
209 tx_rate = rf->p_rate_index;
210 #endif
211 } else /*force rate*/
212 tx_rate = (u8)rate;
213 }
214
215 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Power Tracking tx_rate=0x%X\n",
216 tx_rate);
217 #endif
218
219 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>ODM_TxPwrTrackSetPwr8188F\n");
220
221 if (tx_rate != 0xFF) {
222 /* 2 CCK */
223 if ((tx_rate >= MGN_1M && tx_rate <= MGN_5_5M) || tx_rate == MGN_11M)
224 pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1; /* -2dB */
225 /* 2 OFDM */
226 else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
227 pwr_tracking_limit_ofdm = 36; /* +3dB */
228 else if (tx_rate == MGN_54M)
229 pwr_tracking_limit_ofdm = 34; /* +2dB */
230
231 /* 2 HT */
232 else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2)) /* QPSK/BPSK */
233 pwr_tracking_limit_ofdm = 38; /* +4dB */
234 else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4)) /* 16QAM */
235 pwr_tracking_limit_ofdm = 36; /* +3dB */
236 else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7)) /* 64QAM */
237 pwr_tracking_limit_ofdm = 34; /* +2dB */
238
239 else
240 pwr_tracking_limit_ofdm = cali_info->default_ofdm_index; /* Default OFDM index = 30 */
241 }
242 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "tx_rate=0x%x, pwr_tracking_limit=%d\n",
243 tx_rate, pwr_tracking_limit_ofdm);
244
245 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "method=%d\n", method);
246
247 if (method == TXAGC) {
248 /* u8 rf = 0; */
249 #if (MP_DRIVER == 1)
250 u32 pwr = 0, tx_agc = 0;
251 #endif
252 //void *adapter = dm->adapter;
253
254 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
255 "odm_TxPwrTrackSetPwr8188F CH=%d\n", *(dm->channel));
256
257 cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path];
258
259 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
260
261 #if (MP_DRIVER == 1)
262 if ((*dm->mp_mode) == 1) {
263 pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, MASKBYTE1);
264 pwr += dm->rf_calibrate_info.power_index_offset[RF_PATH_A];
265 odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr); /* CCK 1M */
266
267 if (pwr > 0x3F)
268 pwr = 0x3F; /* add by Mingzhi.Guo 2015-04-10 */
269 else if (pwr <= 0)
270 pwr = 0;
271
272 tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
273
274 odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xffffff00, tx_agc); /* CCK 2~11M */
275 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
276 "ODM_TxPwrTrackSetPwr8188F: CCK Tx-rf(A) Power = 0x%x\n",
277 tx_agc);
278
279 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
280 pwr += (cali_info->bb_swing_idx_ofdm[RF_PATH_A] - cali_info->bb_swing_idx_ofdm_base[RF_PATH_A]);
281 tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
282 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
283 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
284 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
285 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
286 /* odm_set_bb_reg(adapter, REG_TX_AGC_A_MCS11_MCS08, MASKDWORD, tx_agc); */
287 /* odm_set_bb_reg(adapter, REG_TX_AGC_A_MCS15_MCS12, MASKDWORD, tx_agc); */
288 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
289 "ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n",
290 tx_agc);
291 } else
292 #endif
293 {
294 /* PHY_SetTxPowerLevelByPath8188F(adapter, hal_data->current_channel, RF_PATH_A); */
295 /* PHY_SetTxPowerLevel8188F(dm->adapter, *dm->channel); */
296 cali_info->modify_tx_agc_flag_path_a = true;
297 cali_info->modify_tx_agc_flag_path_a_cck = true;
298
299 if (rf_path == RF_PATH_A) {
300 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
301 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, OFDM);
302 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS0_MCS7);
303 }
304 }
305
306 #endif
307 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
308 /* phy_rf6052_set_cck_tx_power(dm->priv, *(dm->channel)); */
309 /* phy_rf6052_set_ofdm_tx_power(dm->priv, *(dm->channel)); */
310 #endif
311
312 } else if (method == BBSWING) {
313 final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
314 final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
315
316 /* Adjust BB swing by OFDM IQ matrix */
317 if (final_ofdm_swing_index >= pwr_tracking_limit_ofdm)
318 final_ofdm_swing_index = pwr_tracking_limit_ofdm;
319 else if (final_ofdm_swing_index <= 0)
320 final_ofdm_swing_index = 0;
321
322 if (final_cck_swing_index >= CCK_TABLE_SIZE_88F)
323 final_cck_swing_index = CCK_TABLE_SIZE_88F - 1;
324 else if ((s8)cali_info->bb_swing_idx_cck < 0)
325 final_cck_swing_index = 0;
326
327 if (rf_path == RF_PATH_A) {
328 set_iqk_matrix_8188f(dm, final_ofdm_swing_index, RF_PATH_A,
329 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
330 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
331 if (*dm->channel != 14) {
332 odm_write_1byte(dm, 0xa22, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][0]);
333 odm_write_1byte(dm, 0xa23, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][1]);
334 odm_write_1byte(dm, 0xa24, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][2]);
335 odm_write_1byte(dm, 0xa25, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][3]);
336 odm_write_1byte(dm, 0xa26, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][4]);
337 odm_write_1byte(dm, 0xa27, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][5]);
338 odm_write_1byte(dm, 0xa28, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][6]);
339 odm_write_1byte(dm, 0xa29, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][7]);
340 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][8]);
341 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][9]);
342 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][10]);
343 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][11]);
344 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][12]);
345 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][13]);
346 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][14]);
347 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][15]);
348 } else {
349 odm_write_1byte(dm, 0xa22, cck_swing_table_ch14_88f[final_cck_swing_index][0]);
350 odm_write_1byte(dm, 0xa23, cck_swing_table_ch14_88f[final_cck_swing_index][1]);
351 odm_write_1byte(dm, 0xa24, cck_swing_table_ch14_88f[final_cck_swing_index][2]);
352 odm_write_1byte(dm, 0xa25, cck_swing_table_ch14_88f[final_cck_swing_index][3]);
353 odm_write_1byte(dm, 0xa26, cck_swing_table_ch14_88f[final_cck_swing_index][4]);
354 odm_write_1byte(dm, 0xa27, cck_swing_table_ch14_88f[final_cck_swing_index][5]);
355 odm_write_1byte(dm, 0xa28, cck_swing_table_ch14_88f[final_cck_swing_index][6]);
356 odm_write_1byte(dm, 0xa29, cck_swing_table_ch14_88f[final_cck_swing_index][7]);
357 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch14_88f[final_cck_swing_index][8]);
358 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch14_88f[final_cck_swing_index][9]);
359 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch14_88f[final_cck_swing_index][10]);
360 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch14_88f[final_cck_swing_index][11]);
361 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch14_88f[final_cck_swing_index][12]);
362 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch14_88f[final_cck_swing_index][13]);
363 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch14_88f[final_cck_swing_index][14]);
364 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch14_88f[final_cck_swing_index][15]);
365 }
366 }
367
368 } else if (method == MIX_MODE) {
369 #if (MP_DRIVER == 1)
370 /* u32 pwr = 0, tx_agc = 0; */
371 u32 tx_agc = 0; /* add by Mingzhi.Guo 2015-04-10 */
372 s32 pwr = 0;
373 /* s32 pwr_down_up = 0; */
374 #endif
375 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "method is MIX_MODE ====>\n");
376 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
377 "cali_info->default_ofdm_index=%d, cali_info->DefaultCCKIndex=%d, cali_info->absolute_ofdm_swing_idx[rf_path]=%d, rf_path = %d\n",
378 cali_info->default_ofdm_index,
379 cali_info->default_cck_index,
380 cali_info->absolute_ofdm_swing_idx[rf_path], rf_path);
381
382 final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
383 final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
384 if (rf_path == RF_PATH_A) {
385 if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) { /* BBSwing higher then Limit */
386 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
387
388 set_iqk_matrix_8188f(dm, pwr_tracking_limit_ofdm, rf_path,
389 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
390 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
391
392 cali_info->modify_tx_agc_flag_path_a = true;
393
394 /* Set tx_agc Page C{}; */
395
396 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
397 "******Path_A Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
398 pwr_tracking_limit_ofdm,
399 cali_info->remnant_ofdm_swing_idx[rf_path
400 ]);
401 } else if (final_ofdm_swing_index < cali_info->default_ofdm_index) {
402 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - cali_info->default_ofdm_index;
403 set_iqk_matrix_8188f(dm, cali_info->default_ofdm_index, RF_PATH_A,
404 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
405 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
406
407 cali_info->modify_tx_agc_flag_path_a = true;
408 /* Set tx_agc Page C{}; */
409
410 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
411 "******Path_A Lower then BBSwing lower bound 28, Remnant tx_agc value = %d\n",
412 cali_info->remnant_ofdm_swing_idx[rf_path
413 ]);
414 }
415
416 #if 0
417 else if (final_ofdm_swing_index < 0) {
418 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index ;
419 set_iqk_matrix_8188f(dm, 0, RF_PATH_A,
420 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
421 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
422
423 cali_info->modify_tx_agc_flag_path_a = true;
424 /* Set tx_agc Page C{}; */
425
426 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
427 "******Path_A Lower then BBSwing lower bound 0, Remnant tx_agc value = %d\n",
428 cali_info->remnant_ofdm_swing_idx[rf_path
429 ]);
430 }
431 #endif
432 else {
433 set_iqk_matrix_8188f(dm, final_ofdm_swing_index, RF_PATH_A,
434 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
435 dm->rf_calibrate_info.iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
436
437 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
438 "******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n",
439 final_ofdm_swing_index);
440
441 if (cali_info->modify_tx_agc_flag_path_a) /* If tx_agc has changed, reset tx_agc again */
442 cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
443 }
444 #if (MP_DRIVER == 1) && (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
445 if ((*dm->mp_mode) == 1) {
446 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
447 /* pwr_down_up = (cali_info->remnant_ofdm_swing_idx[RF_PATH_A] - cali_info->modify_tx_agc_value_ofdm); */
448 pwr += (cali_info->remnant_ofdm_swing_idx[RF_PATH_A] - cali_info->modify_tx_agc_value_ofdm);
449
450 if (pwr > 0x3F)
451 pwr = 0x3F; /* add by Mingzhi.Guo 2015-04-10 */
452 else if (pwr < 0)
453 pwr = 0;
454
455 #if 0
456 if (pwr == 0x32 || pwr == 0x33) { /*8188F TXAGC skip index 32&33 to avoid bad TX EVM, suggested by RF_Jayden*/
457 if (pwr_down_up >= 0)
458 pwr = 0x34;
459 else
460 pwr = 0x31;
461 }
462 #endif
463
464 tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
465 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
466 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
467 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
468 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
469 /* odm_set_bb_reg(dm, REG_TX_AGC_A_MCS11_MCS08, MASKDWORD, tx_agc); */
470 /* odm_set_bb_reg(dm, REG_TX_AGC_A_MCS15_MCS12, MASKDWORD, tx_agc); */
471 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
472 "ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n",
473 tx_agc);
474
475 } else
476 #endif
477 {
478 /* Set tx_agc Page C{}; */
479 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, OFDM);
480 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS0_MCS7);
481 }
482 cali_info->modify_tx_agc_value_ofdm = cali_info->remnant_ofdm_swing_idx[RF_PATH_A]; /* add by Mingzhi.Guo */
483
484 /* MIX mode: CCK */
485 if (final_cck_swing_index > pwr_tracking_limit_cck) {
486 cali_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit_cck;
487 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
488 "******Path_A CCK Over Limit, pwr_tracking_limit_cck = %d, cali_info->remnant_cck_swing_idx = %d\n",
489 pwr_tracking_limit_cck,
490 cali_info->remnant_cck_swing_idx);
491 if (*dm->channel != 14) {
492 odm_write_1byte(dm, 0xa22, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][0]);
493 odm_write_1byte(dm, 0xa23, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][1]);
494 odm_write_1byte(dm, 0xa24, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][2]);
495 odm_write_1byte(dm, 0xa25, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][3]);
496 odm_write_1byte(dm, 0xa26, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][4]);
497 odm_write_1byte(dm, 0xa27, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][5]);
498 odm_write_1byte(dm, 0xa28, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][6]);
499 odm_write_1byte(dm, 0xa29, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][7]);
500 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][8]);
501 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][9]);
502 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][10]);
503 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][11]);
504 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][12]);
505 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][13]);
506 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][14]);
507 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch1_ch13_88f[pwr_tracking_limit_cck][15]);
508 } else {
509 odm_write_1byte(dm, 0xa22, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][0]);
510 odm_write_1byte(dm, 0xa23, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][1]);
511 odm_write_1byte(dm, 0xa24, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][2]);
512 odm_write_1byte(dm, 0xa25, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][3]);
513 odm_write_1byte(dm, 0xa26, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][4]);
514 odm_write_1byte(dm, 0xa27, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][5]);
515 odm_write_1byte(dm, 0xa28, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][6]);
516 odm_write_1byte(dm, 0xa29, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][7]);
517 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][8]);
518 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][9]);
519 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][10]);
520 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][11]);
521 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][12]);
522 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][13]);
523 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][14]);
524 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch14_88f[pwr_tracking_limit_cck][15]);
525 }
526
527 cali_info->modify_tx_agc_flag_path_a_cck = true;
528
529 } else if (final_cck_swing_index < 0) { /* Lowest CCK index = 0 */
530 cali_info->remnant_cck_swing_idx = final_cck_swing_index;
531
532 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
533 "******Path_A CCK Under Limit, pwr_tracking_limit_cck = %d, cali_info->remnant_cck_swing_idx = %d\n",
534 0, cali_info->remnant_cck_swing_idx);
535 if (*dm->channel != 14) {
536 odm_write_1byte(dm, 0xa22, cck_swing_table_ch1_ch13_88f[0][0]);
537 odm_write_1byte(dm, 0xa23, cck_swing_table_ch1_ch13_88f[0][1]);
538 odm_write_1byte(dm, 0xa24, cck_swing_table_ch1_ch13_88f[0][2]);
539 odm_write_1byte(dm, 0xa25, cck_swing_table_ch1_ch13_88f[0][3]);
540 odm_write_1byte(dm, 0xa26, cck_swing_table_ch1_ch13_88f[0][4]);
541 odm_write_1byte(dm, 0xa27, cck_swing_table_ch1_ch13_88f[0][5]);
542 odm_write_1byte(dm, 0xa28, cck_swing_table_ch1_ch13_88f[0][6]);
543 odm_write_1byte(dm, 0xa29, cck_swing_table_ch1_ch13_88f[0][7]);
544 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch1_ch13_88f[0][8]);
545 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch1_ch13_88f[0][9]);
546 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch1_ch13_88f[0][10]);
547 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch1_ch13_88f[0][11]);
548 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch1_ch13_88f[0][12]);
549 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch1_ch13_88f[0][13]);
550 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch1_ch13_88f[0][14]);
551 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch1_ch13_88f[0][15]);
552 } else {
553 odm_write_1byte(dm, 0xa22, cck_swing_table_ch14_88f[0][0]);
554 odm_write_1byte(dm, 0xa23, cck_swing_table_ch14_88f[0][1]);
555 odm_write_1byte(dm, 0xa24, cck_swing_table_ch14_88f[0][2]);
556 odm_write_1byte(dm, 0xa25, cck_swing_table_ch14_88f[0][3]);
557 odm_write_1byte(dm, 0xa26, cck_swing_table_ch14_88f[0][4]);
558 odm_write_1byte(dm, 0xa27, cck_swing_table_ch14_88f[0][5]);
559 odm_write_1byte(dm, 0xa28, cck_swing_table_ch14_88f[0][6]);
560 odm_write_1byte(dm, 0xa29, cck_swing_table_ch14_88f[0][7]);
561 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch14_88f[0][8]);
562 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch14_88f[0][9]);
563 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch14_88f[0][10]);
564 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch14_88f[0][11]);
565 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch14_88f[0][12]);
566 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch14_88f[0][13]);
567 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch14_88f[0][14]);
568 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch14_88f[0][15]);
569 }
570 cali_info->modify_tx_agc_flag_path_a_cck = true;
571 }
572
573 else {
574 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
575 "******Path_A CCK Compensate with BBSwing, final_cck_swing_index = %d\n",
576 final_cck_swing_index);
577 if (*dm->channel != 14) {
578 odm_write_1byte(dm, 0xa22, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][0]);
579 odm_write_1byte(dm, 0xa23, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][1]);
580 odm_write_1byte(dm, 0xa24, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][2]);
581 odm_write_1byte(dm, 0xa25, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][3]);
582 odm_write_1byte(dm, 0xa26, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][4]);
583 odm_write_1byte(dm, 0xa27, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][5]);
584 odm_write_1byte(dm, 0xa28, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][6]);
585 odm_write_1byte(dm, 0xa29, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][7]);
586 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][8]);
587 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][9]);
588 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][10]);
589 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][11]);
590 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][12]);
591 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][13]);
592 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][14]);
593 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch1_ch13_88f[final_cck_swing_index][15]);
594 } else {
595 odm_write_1byte(dm, 0xa22, cck_swing_table_ch14_88f[final_cck_swing_index][0]);
596 odm_write_1byte(dm, 0xa23, cck_swing_table_ch14_88f[final_cck_swing_index][1]);
597 odm_write_1byte(dm, 0xa24, cck_swing_table_ch14_88f[final_cck_swing_index][2]);
598 odm_write_1byte(dm, 0xa25, cck_swing_table_ch14_88f[final_cck_swing_index][3]);
599 odm_write_1byte(dm, 0xa26, cck_swing_table_ch14_88f[final_cck_swing_index][4]);
600 odm_write_1byte(dm, 0xa27, cck_swing_table_ch14_88f[final_cck_swing_index][5]);
601 odm_write_1byte(dm, 0xa28, cck_swing_table_ch14_88f[final_cck_swing_index][6]);
602 odm_write_1byte(dm, 0xa29, cck_swing_table_ch14_88f[final_cck_swing_index][7]);
603 odm_write_1byte(dm, 0xa9a, cck_swing_table_ch14_88f[final_cck_swing_index][8]);
604 odm_write_1byte(dm, 0xa9b, cck_swing_table_ch14_88f[final_cck_swing_index][9]);
605 odm_write_1byte(dm, 0xa9c, cck_swing_table_ch14_88f[final_cck_swing_index][10]);
606 odm_write_1byte(dm, 0xa9d, cck_swing_table_ch14_88f[final_cck_swing_index][11]);
607 odm_write_1byte(dm, 0xaa0, cck_swing_table_ch14_88f[final_cck_swing_index][12]);
608 odm_write_1byte(dm, 0xaa1, cck_swing_table_ch14_88f[final_cck_swing_index][13]);
609 odm_write_1byte(dm, 0xaa2, cck_swing_table_ch14_88f[final_cck_swing_index][14]);
610 odm_write_1byte(dm, 0xaa3, cck_swing_table_ch14_88f[final_cck_swing_index][15]);
611 }
612
613 cali_info->modify_tx_agc_flag_path_a_cck = false;
614 cali_info->remnant_cck_swing_idx = 0;
615 }
616 #if (MP_DRIVER == 1) && (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
617 if ((*dm->mp_mode) == 1) {
618 pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, MASKBYTE1);
619 pwr += cali_info->remnant_cck_swing_idx - cali_info->modify_tx_agc_value_cck;
620
621 if (pwr > 0x3F)
622 pwr = 0x3F; /* add by Mingzhi.Guo 2015-04-10 */
623 else if (pwr < 0)
624 pwr = 0;
625
626 odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr); /* CCK 1M */
627 tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
628 odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xffffff00, tx_agc); /* CCK 2~11M */
629 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
630 "ODM_TxPwrTrackSetPwr8188F: CCK Tx-rf(A) Power = 0x%x\n",
631 tx_agc);
632 } else
633 #endif
634 {
635 /* Set tx_agc Page C{}; */
636 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
637 }
638 cali_info->modify_tx_agc_value_cck = cali_info->remnant_cck_swing_idx;
639 }
640 } else
641 return;
642 } /* odm_TxPwrTrackSetPwr8188F */
643
get_delta_swing_table_8188f(void * dm_void,u8 ** temperature_up_a,u8 ** temperature_down_a,u8 ** temperature_up_b,u8 ** temperature_down_b)644 void get_delta_swing_table_8188f(void *dm_void, u8 **temperature_up_a,
645 u8 **temperature_down_a, u8 **temperature_up_b,
646 u8 **temperature_down_b)
647 {
648 struct dm_struct *dm = (struct dm_struct *)dm_void;
649 struct _ADAPTER *adapter = dm->adapter;
650 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
651 struct _hal_rf_ *rf = &(dm->rf_table);
652 u8 tx_rate = 0xFF;
653 u8 channel = *dm->channel;
654
655 if (*dm->mp_mode == true) {
656 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
657 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
658 #if (MP_DRIVER == 1)
659 PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
660
661 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
662 #endif
663 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
664 #ifdef CONFIG_MP_INCLUDED
665 PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
666
667 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
668 #endif
669 #endif
670 #endif
671 } else {
672 u16 rate = *(dm->forced_data_rate);
673
674 if (!rate) { /*auto rate*/
675 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
676 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
677 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
678 if (dm->number_linked_client != 0)
679 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
680 else
681 tx_rate = rf->p_rate_index;
682 #endif
683 } else /*force rate*/
684 tx_rate = (u8)rate;
685 }
686
687 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Power Tracking tx_rate=0x%X\n",
688 tx_rate);
689
690 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "%s ====> channel is %d\n", __func__,
691 channel);
692
693 if (1 <= channel && channel <= 14) {
694 if (IS_CCK_RATE(tx_rate)) {
695 *temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
696 *temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
697 *temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
698 *temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
699 } else {
700 *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
701 *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
702 *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
703 *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
704 }
705 } else {
706 *temperature_up_a = (u8 *)delta_swing_table_idx_2ga_p_8188e;
707 *temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
708 *temperature_up_b = (u8 *)delta_swing_table_idx_2ga_p_8188e;
709 *temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
710 }
711
712 return;
713 }
714
configure_txpower_track_8188f(struct txpwrtrack_cfg * config)715 void configure_txpower_track_8188f(struct txpwrtrack_cfg *config)
716 {
717 config->swing_table_size_cck = CCK_TABLE_SIZE_88F;
718 config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
719 config->threshold_iqk = IQK_THRESHOLD;
720 config->average_thermal_num = AVG_THERMAL_NUM_8188F;
721 config->rf_path_count = MAX_PATH_NUM_8188F;
722 config->thermal_reg_addr = RF_T_METER_8188F;
723
724 config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr_8188f;
725 config->do_iqk = do_iqk_8188f;
726 config->phy_lc_calibrate = halrf_lck_trigger;
727 config->get_delta_swing_table = get_delta_swing_table_8188f;
728 }
729
730 /* 1 7. IQK */
731 #define MAX_TOLERANCE 5
732 #define IQK_DELAY_TIME 1 /* ms */
733
734 u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_path_a_iqk_8188f(struct dm_struct * dm,boolean config_path_b)735 phy_path_a_iqk_8188f(
736 struct dm_struct *dm,
737 boolean config_path_b)
738 {
739 u32 reg_eac, reg_e94, reg_e9c /*, reg_ea4*/;
740 u8 result = 0x00;
741 RF_DBG(dm, DBG_RF_IQK, "path A IQK!\n");
742
743 /* enable path A PA in TXIQK mode */
744 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
745 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
746 odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x20000);
747 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x0000f);
748 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0x07ff7); /* 0x07f77 */
749 /* PA,PAD gain adjust */
750 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x980);
751 odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, RFREGOFFSETMASK, 0x5102a); /* 0x5111e0 */
752
753 /* enter IQK mode */
754 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000);
755
756 /* 1 Tx IQK */
757 /* path-A IQK setting
758 * RF_DBG(dm,DBG_RF_IQK, "path-A IQK setting!\n"); */
759 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
760 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
761 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x821403ff); /* 0x821403e0 */
762 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28160000);
763
764 /* LO calibration setting
765 * RF_DBG(dm,DBG_RF_IQK, "LO calibration setting!\n"); */
766 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x00462911);
767
768 /* One shot, path A LOK & IQK
769 * RF_DBG(dm,DBG_RF_IQK, "One shot, path A LOK & IQK!\n"); */
770 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
771 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
772
773 /* delay x ms
774 * RF_DBG(dm,DBG_RF_IQK, "delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F);
775 * platform_stall_execution(IQK_DELAY_TIME_8188F*1000); */
776 ODM_delay_ms(IQK_DELAY_TIME_8188F);
777
778 /* reload RF 0xdf */
779 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
780 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x180);
781
782 /* save LOK result */
783 dm->rf_calibrate_info.lok_result = odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK);
784
785 /* Check failed */
786 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
787 reg_e94 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
788 reg_e9c = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
789 RF_DBG(dm, DBG_RF_IQK, "0xeac = 0x%x\n", reg_eac);
790 RF_DBG(dm, DBG_RF_IQK, "0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
791 reg_e9c);
792 /* monitor image power before & after IQK */
793 RF_DBG(dm, DBG_RF_IQK,
794 "0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
795 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
796 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
797
798 if (!(reg_eac & BIT(28)) &&
799 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
800 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
801 result |= 0x01;
802
803 return result;
804 }
805
806 u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_path_a_rx_iqk_8188f(struct dm_struct * dm,boolean config_path_b)807 phy_path_a_rx_iqk_8188f(
808 struct dm_struct *dm,
809 boolean config_path_b)
810 {
811 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp;
812 u8 result = 0x00;
813 RF_DBG(dm, DBG_RF_IQK, "path A Rx IQK!\n");
814
815 /* 1 Get TXIMR setting */
816 /* modify RXIQK mode table
817 * RF_DBG(dm,DBG_RF_IQK, "path-A Rx IQK modify RXIQK mode table!\n"); */
818 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
819 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
820 odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000);
821 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x0000f);
822 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf1173); /* 0xf117b */
823
824 /* PA,PAD gain adjust */
825 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x980);
826 odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, RFREGOFFSETMASK, 0x5102a); /* 0x510f0 */
827
828 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000);
829
830 /* IQK setting */
831 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
832 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
833
834 /* path-A IQK setting */
835 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
836 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
837 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82160fff); /* 0x821603e0 */
838 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28160000);
839
840 /* LO calibration setting
841 * RF_DBG(dm,DBG_RF_IQK, "LO calibration setting!\n"); */
842 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x00462911);
843
844 /* One shot, path A LOK & IQK
845 * RF_DBG(dm,DBG_RF_IQK, "One shot, path A LOK & IQK!\n"); */
846 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
847 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
848
849 /* delay x ms
850 * RF_DBG(dm,DBG_RF_IQK, "delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F);
851 * platform_stall_execution(IQK_DELAY_TIME_8188F*1000); */
852 ODM_delay_ms(IQK_DELAY_TIME_8188F);
853
854 /* reload RF 0xdf */
855 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
856 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x180);
857
858 /* Check failed */
859 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
860 reg_e94 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
861 reg_e9c = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
862 RF_DBG(dm, DBG_RF_IQK, "0xeac = 0x%x\n", reg_eac);
863 RF_DBG(dm, DBG_RF_IQK, "0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
864 reg_e9c);
865 /* monitor image power before & after IQK */
866 RF_DBG(dm, DBG_RF_IQK,
867 "0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
868 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
869 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
870
871 if (!(reg_eac & BIT(28)) &&
872 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
873 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
874 result |= 0x01;
875 else /* if Tx not OK, ignore Rx */
876 return result;
877
878 u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | ((reg_e9c & 0x3FF0000) >> 16);
879 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, u4tmp);
880 RF_DBG(dm, DBG_RF_IQK, "0xe40 = 0x%x u4tmp = 0x%x\n",
881 odm_get_bb_reg(dm, REG_TX_IQK, MASKDWORD), u4tmp);
882
883 /* 1 RX IQK */
884 /* modify RXIQK mode table
885 * RF_DBG(dm,DBG_RF_IQK, "path-A Rx IQK modify RXIQK mode table 2!\n"); */
886 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
887 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /* 0xEF[19] = 0x1 */
888 odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000); /* 0x30[19:0] = 0x18000 */
889 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x0000f); /* 0x31[19:0] = 0x0000f */
890 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7ff2); /* 0x32[19:0] = 0xf7ffa */
891
892 /* PA,PAD gain adjust */
893 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x980);
894 odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, RFREGOFFSETMASK, 0x51000); /* 0x51000 */
895
896 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000);
897
898 /* IQK setting */
899 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
900
901 /* path-A IQK setting */
902 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
903 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
904 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82160000);
905 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x281613ff); /* 0x281603e0 */
906
907 /* LO calibration setting
908 * RF_DBG(dm,DBG_RF_IQK, "LO calibration setting!\n"); */
909 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a911);
910
911 /* One shot, path A LOK & IQK
912 * RF_DBG(dm,DBG_RF_IQK, "One shot, path A LOK & IQK!\n"); */
913 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
914 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
915
916 /* delay x ms
917 * RF_DBG(dm,DBG_RF_IQK, "delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F);
918 * platform_stall_execution(IQK_DELAY_TIME_8188F*1000); */
919 ODM_delay_ms(IQK_DELAY_TIME_8188F);
920
921 /* reload RF 0xdf */
922 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
923 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x180);
924
925 /* reload LOK value */
926 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK, dm->rf_calibrate_info.lok_result);
927
928 /* Check failed */
929 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
930 reg_ea4 = odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
931 RF_DBG(dm, DBG_RF_IQK, "0xeac = 0x%x\n", reg_eac);
932 RF_DBG(dm, DBG_RF_IQK, "0xea4 = 0x%x, 0xeac = 0x%x\n", reg_ea4,
933 reg_eac);
934 /* monitor image power before & after IQK */
935 RF_DBG(dm, DBG_RF_IQK,
936 "0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
937 odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
938 odm_get_bb_reg(dm, R_0xea8, MASKDWORD));
939
940 if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
941 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
942 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
943 result |= 0x02;
944 else
945 RF_DBG(dm, DBG_RF_IQK, "path A Rx IQK fail!!\n");
946
947 return result;
948 }
949
950 #if 0
951 u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
952 phy_path_b_iqk_8188f(
953 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
954 struct dm_struct *dm
955 #else
956 void *adapter
957 #endif
958 )
959 {
960 u32 reg_eac, reg_e94, reg_e9c/*, reg_ec4, reg_ecc*/;
961 u8 result = 0x00;
962 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
963 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
964 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
965 struct dm_struct *dm = &hal_data->odmpriv;
966 #endif
967 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
968 struct dm_struct *dm = &hal_data->DM_OutSrc;
969 #endif
970 #endif
971 RF_DBG(dm, DBG_RF_IQK, "path B IQK!\n");
972
973 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
974 /* switch to path B */
975 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000080);
976 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0xefff0);
977 /* in TXIQK mode
978 * odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, RFREGOFFSETMASK, 0x800a0 );
979 * odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x20000 );
980 * odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x0003f );
981 * odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xc7f87 );
982 * enable path B PA in TXIQK mode
983 * odm_set_rf_reg(dm, RF_PATH_A, RF_0xed, RFREGOFFSETMASK, 0x00020 );
984 * odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, RFREGOFFSETMASK, 0x40fc1 ); */
985
986
987 /* 1 Tx IQK */
988 /* path-A IQK setting
989 * RF_DBG(dm,DBG_RF_IQK, "path-B IQK setting!\n"); */
990 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
991 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
992 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82140102);
993 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28160000);
994
995 /* LO calibration setting
996 * RF_DBG(dm,DBG_RF_IQK, "LO calibration setting!\n"); */
997 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x00462911);
998
999
1000 /* enter IQK mode */
1001 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000);
1002
1003 /* One shot, path B LOK & IQK
1004 * RF_DBG(dm,DBG_RF_IQK, "One shot, path B LOK & IQK!\n"); */
1005 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
1006 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
1007
1008 /* delay x ms
1009 * RF_DBG(dm,DBG_RF_IQK, "delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_8188F);
1010 * platform_stall_execution(IQK_DELAY_TIME_8188F*1000); */
1011 ODM_delay_ms(IQK_DELAY_TIME_8188F);
1012
1013 RF_DBG(dm, DBG_RF_IQK, "0x948 = 0x%x\n",
1014 odm_get_bb_reg(dm, R_0x948, MASKDWORD));
1015
1016
1017 /* Check failed */
1018 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
1019 reg_e94 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
1020 reg_e9c = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
1021 RF_DBG(dm, DBG_RF_IQK, "0xeac = 0x%x\n", reg_eac);
1022 RF_DBG(dm, DBG_RF_IQK, "0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
1023 reg_e9c);
1024 /* monitor image power before & after IQK */
1025 RF_DBG(dm, DBG_RF_IQK,
1026 "0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
1027 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
1028 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
1029
1030
1031 if (!(reg_eac & BIT(28)) &&
1032 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1033 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1034 result |= 0x01;
1035 else
1036 return result;
1037 #if 0
1038 if (!(reg_eac & BIT(30)) &&
1039 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1040 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1041 result |= 0x02;
1042 else
1043 RF_DBG(dm, DBG_RF_IQK, "path B Rx IQK fail!!\n");
1044
1045 #endif
1046 return result;
1047 }
1048
1049
1050
1051 u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1052 phy_path_b_rx_iqk_8188f(
1053 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1054 struct dm_struct *dm,
1055 #else
1056 void *adapter,
1057 #endif
1058 boolean config_path_b
1059 )
1060 {
1061 u32 reg_eac, reg_eb4, reg_ebc, reg_ecc, reg_ec4, u4tmp;
1062 u8 result = 0x00;
1063 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1064 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1065 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1066 struct dm_struct *dm = &hal_data->odmpriv;
1067 #endif
1068 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1069 struct dm_struct *dm = &hal_data->DM_OutSrc;
1070 #endif
1071 #endif
1072 RF_DBG(dm, DBG_RF_IQK, "path B Rx IQK!\n");
1073
1074 /* 1 Get TXIMR setting */
1075 RF_DBG(dm, DBG_RF_IQK, "Get RXIQK TXIMR!\n");
1076 /* modify RXIQK mode table
1077 * RF_DBG(dm,DBG_RF_IQK, "path-A Rx IQK modify RXIQK mode table!\n");
1078 * odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
1079 * odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, RFREGOFFSETMASK, 0x800a0 );
1080 * odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000 );
1081 * odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x0000f );
1082 * odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf117B );
1083 * odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); */
1084
1085 /* IQK setting */
1086 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
1087 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x81004800);
1088
1089 /* path-B IQK setting */
1090 odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x10008c1c);
1091 odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x30008c1c);
1092 odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82130804);
1093 odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x68130000);
1094
1095 /* LO calibration setting */
1096 RF_DBG(dm, DBG_RF_IQK, "LO calibration setting!\n");
1097 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a911);
1098
1099 /* One shot, path B LOK & IQK */
1100 RF_DBG(dm, DBG_RF_IQK, "One shot, path B LOK & IQK!\n");
1101 odm_set_bb_reg(dm, REG_IQK_AGC_CONT, MASKDWORD, 0x00000002);
1102 odm_set_bb_reg(dm, REG_IQK_AGC_CONT, MASKDWORD, 0x00000000);
1103
1104 /* delay x ms */
1105 RF_DBG(dm, DBG_RF_IQK, "delay %d ms for One shot, path A LOK & IQK.\n",
1106 IQK_DELAY_TIME_8188F);
1107 /* platform_stall_execution(IQK_DELAY_TIME_8188F*1000); */
1108 ODM_delay_ms(IQK_DELAY_TIME_8188F);
1109
1110
1111 /* Check failed */
1112 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
1113 reg_eb4 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD);
1114 reg_ebc = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_B, MASKDWORD);
1115 RF_DBG(dm, DBG_RF_IQK, "0xeac = 0x%x\n", reg_eac);
1116 RF_DBG(dm, DBG_RF_IQK, "0xeb4 = 0x%x, 0xebc = 0x%x\n", reg_eb4,
1117 reg_ebc);
1118 /* monitor image power before & after IQK */
1119 RF_DBG(dm, DBG_RF_IQK,
1120 "0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n",
1121 odm_get_bb_reg(dm, R_0xeb0, MASKDWORD),
1122 odm_get_bb_reg(dm, R_0xeb8, MASKDWORD));
1123
1124
1125 if (!(reg_eac & BIT(31)) &&
1126 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1127 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1128 result |= 0x01;
1129 else /* if Tx not OK, ignore Rx */
1130 return result;
1131
1132 u4tmp = 0x80007C00 | (reg_eb4 & 0x3FF0000) | ((reg_ebc & 0x3FF0000) >> 16);
1133 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, u4tmp);
1134 RF_DBG(dm, DBG_RF_IQK, "0xe40 = 0x%x u4tmp = 0x%x\n",
1135 odm_get_bb_reg(dm, REG_TX_IQK, MASKDWORD), u4tmp);
1136
1137
1138 /* 1 RX IQK */
1139 /* modify RXIQK mode table
1140 * RF_DBG(dm,DBG_RF_IQK, "path-A Rx IQK modify RXIQK mode table 2!\n");
1141 * odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
1142 * odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, RFREGOFFSETMASK, 0x800a0 ); */
1143
1144 /* <20121009, Kordan> RF mode = 3
1145 * odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */ /* 0xEF[19] = 0x1
1146 * odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x18000 ); */ /* 0x30[19:0] = 0x18000
1147 * odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x0000f ); */ /* 0x31[19:0] = 0x0000f
1148 * odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7ffa ); */ /* 0x32[19:0] = 0xf7ffa
1149 * odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ /* 0xEF[19] = 0x0
1150 * odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000); */
1151
1152 /* IQK setting */
1153 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
1154
1155 /* path-B IQK setting */
1156 odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x30008c1c);
1157 odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x10008c1c);
1158 odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82130c05);
1159 odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x68130c05);
1160
1161 /* LO calibration setting */
1162 RF_DBG(dm, DBG_RF_IQK, "LO calibration setting!\n");
1163 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a911);
1164
1165 /* One shot, path B LOK & IQK */
1166 RF_DBG(dm, DBG_RF_IQK, "One shot, path B LOK & IQK!\n");
1167 odm_set_bb_reg(dm, REG_IQK_AGC_CONT, MASKDWORD, 0x00000002);
1168 odm_set_bb_reg(dm, REG_IQK_AGC_CONT, MASKDWORD, 0x00000000);
1169
1170 /* delay x ms */
1171 RF_DBG(dm, DBG_RF_IQK, "delay %d ms for One shot, path A LOK & IQK.\n",
1172 IQK_DELAY_TIME_8188F);
1173 /* platform_stall_execution(IQK_DELAY_TIME_8188F*1000); */
1174 ODM_delay_ms(IQK_DELAY_TIME_8188F);
1175
1176 /* Check failed */
1177 reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
1178 reg_ec4 = odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_B_2, MASKDWORD);;
1179 reg_ecc = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_B_2, MASKDWORD);
1180 RF_DBG(dm, DBG_RF_IQK, "0xeac = 0x%x\n", reg_eac);
1181 RF_DBG(dm, DBG_RF_IQK, "0xec4 = 0x%x, 0xecc = 0x%x\n", reg_ec4,
1182 reg_ecc);
1183 /* monitor image power before & after IQK */
1184 RF_DBG(dm, DBG_RF_IQK,
1185 "0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n",
1186 odm_get_bb_reg(dm, R_0xec0, MASKDWORD),
1187 odm_get_bb_reg(dm, R_0xec8, MASKDWORD));
1188
1189 /* PA/PAD controlled by 0x0 */
1190 /* leave IQK mode
1191 * odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
1192 * odm_set_rf_reg(dm, RF_PATH_B, RF_0xdf, RFREGOFFSETMASK, 0x180 ); */
1193
1194 #if 0
1195 if (!(reg_eac & BIT(31)) &&
1196 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1197 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1198 result |= 0x01;
1199 else /* if Tx not OK, ignore Rx */
1200 return result;
1201 #endif
1202
1203 if (!(reg_eac & BIT(30)) && /* if Tx is OK, check whether Rx is OK */
1204 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1205 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1206 result |= 0x02;
1207 else
1208 RF_DBG(dm, DBG_RF_IQK, "path B Rx IQK fail!!\n");
1209
1210 return result;
1211 }
1212 #endif
1213
_phy_path_a_fill_iqk_matrix8188f(struct dm_struct * dm,boolean is_iqk_ok,s32 result[][8],u8 final_candidate,boolean is_tx_only)1214 void _phy_path_a_fill_iqk_matrix8188f(struct dm_struct *dm, boolean is_iqk_ok,
1215 s32 result[][8], u8 final_candidate,
1216 boolean is_tx_only)
1217 {
1218 u32 oldval_0, X, TX0_A, reg;
1219 s32 Y, TX0_C;
1220 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1221
1222 RF_DBG(dm, DBG_RF_IQK, "path A IQ Calibration %s !\n",
1223 (is_iqk_ok) ? "Success" : "Failed");
1224
1225 if (final_candidate == 0xFF)
1226 return;
1227
1228 else if (is_iqk_ok) {
1229 oldval_0 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
1230
1231 X = result[final_candidate][0];
1232 if ((X & 0x00000200) != 0)
1233 X = X | 0xFFFFFC00;
1234 TX0_A = (X * oldval_0) >> 8;
1235 RF_DBG(dm, DBG_RF_IQK,
1236 "X = 0x%x, TX0_A = 0x%x, oldval_0 0x%x\n", X, TX0_A,
1237 oldval_0);
1238 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x3FF, TX0_A);
1239
1240 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(31), ((X * oldval_0 >> 7) & 0x1));
1241
1242 Y = result[final_candidate][1];
1243 if ((Y & 0x00000200) != 0)
1244 Y = Y | 0xFFFFFC00;
1245
1246 /* 2 Tx IQC */
1247 TX0_C = (Y * oldval_0) >> 8;
1248 RF_DBG(dm, DBG_RF_IQK, "Y = 0x%x, TX = 0x%x\n", Y, TX0_C);
1249 odm_set_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6));
1250 cali_info->tx_iqc_8723b[PATH_S1][idx_0xc94][KEY] = REG_OFDM_0_XC_TX_AFE;
1251 cali_info->tx_iqc_8723b[PATH_S1][idx_0xc94][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKDWORD);
1252
1253 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x003F0000, (TX0_C & 0x3F));
1254 cali_info->tx_iqc_8723b[PATH_S1][idx_0xc80][KEY] = REG_OFDM_0_XA_TX_IQ_IMBALANCE;
1255 cali_info->tx_iqc_8723b[PATH_S1][idx_0xc80][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD);
1256
1257 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(29), ((Y * oldval_0 >> 7) & 0x1));
1258 cali_info->tx_iqc_8723b[PATH_S1][idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
1259 cali_info->tx_iqc_8723b[PATH_S1][idx_0xc4c][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD);
1260
1261 if (is_tx_only) {
1262 RF_DBG(dm, DBG_RF_IQK, "%s only Tx OK\n", __func__);
1263
1264 /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
1265 cali_info->rx_iqc_8723b[PATH_S1][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1266 cali_info->rx_iqc_8723b[PATH_S1][idx_0xca0][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
1267 cali_info->rx_iqc_8723b[PATH_S1][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1268 cali_info->rx_iqc_8723b[PATH_S1][idx_0xc14][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XA_RX_IQ_IMBALANCE, MASKDWORD);
1269 return;
1270 }
1271
1272 reg = result[final_candidate][2];
1273 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1274 if (RTL_ABS(reg, 0x100) >= 16)
1275 reg = 0x100;
1276 #endif
1277
1278 /* 2 Rx IQC */
1279 odm_set_bb_reg(dm, REG_OFDM_0_XA_RX_IQ_IMBALANCE, 0x3FF, reg);
1280 reg = result[final_candidate][3] & 0x3F;
1281 odm_set_bb_reg(dm, REG_OFDM_0_XA_RX_IQ_IMBALANCE, 0xFC00, reg);
1282 cali_info->rx_iqc_8723b[PATH_S1][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1283 cali_info->rx_iqc_8723b[PATH_S1][idx_0xc14][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XA_RX_IQ_IMBALANCE, MASKDWORD);
1284
1285 reg = (result[final_candidate][3] >> 6) & 0xF;
1286 odm_set_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, 0xF0000000, reg);
1287 cali_info->rx_iqc_8723b[PATH_S1][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1288 cali_info->rx_iqc_8723b[PATH_S1][idx_0xca0][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
1289 }
1290 }
1291
1292 #if 0
1293 void
1294 _phy_path_b_fill_iqk_matrix8188f(
1295 struct dm_struct *dm,
1296 boolean is_iqk_ok,
1297 s32 result[][8],
1298 u8 final_candidate,
1299 boolean is_tx_only /* do Tx only */
1300 )
1301 {
1302 u32 oldval_1, X, TX1_A, reg;
1303 s32 Y, TX1_C;
1304 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1305
1306 RF_DBG(dm, DBG_RF_IQK, "path B IQ Calibration %s !\n",
1307 (is_iqk_ok) ? "Success" : "Failed");
1308
1309 if (final_candidate == 0xFF)
1310 return;
1311
1312 else if (is_iqk_ok) {
1313 oldval_1 = (odm_get_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
1314
1315 X = result[final_candidate][4];
1316 if ((X & 0x00000200) != 0)
1317 X = X | 0xFFFFFC00;
1318 TX1_A = (X * oldval_1) >> 8;
1319 RF_DBG(dm, DBG_RF_IQK, "X = 0x%x, TX1_A = 0x%x\n", X, TX1_A);
1320
1321 odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, 0x3FF, TX1_A);
1322
1323 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(27), ((X * oldval_1 >> 7) & 0x1));
1324
1325 Y = result[final_candidate][5];
1326 if ((Y & 0x00000200) != 0)
1327 Y = Y | 0xFFFFFC00;
1328
1329 TX1_C = (Y * oldval_1) >> 8;
1330 RF_DBG(dm, DBG_RF_IQK, "Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C);
1331
1332 /* 2 Tx IQC */
1333 odm_set_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6));
1334 cali_info->tx_iqc_8723b[PATH_S0][idx_0xc9c][KEY] = REG_OFDM_0_XD_TX_AFE;
1335 cali_info->tx_iqc_8723b[PATH_S0][idx_0xc9c][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, MASKDWORD);
1336
1337 odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, 0x003F0000, (TX1_C & 0x3F));
1338 cali_info->tx_iqc_8723b[PATH_S0][idx_0xc88][KEY] = REG_OFDM_0_XB_TX_IQ_IMBALANCE;
1339 cali_info->tx_iqc_8723b[PATH_S0][idx_0xc88][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD);
1340
1341 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(25), ((Y * oldval_1 >> 7) & 0x1));
1342 cali_info->tx_iqc_8723b[PATH_S0][idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
1343 cali_info->tx_iqc_8723b[PATH_S0][idx_0xc4c][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD);
1344
1345 if (is_tx_only) {
1346 RF_DBG(dm, DBG_RF_IQK, "%s only Tx OK\n", __func__);
1347
1348 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc1c][KEY] = REG_OFDM_0_XB_RX_IQ_IMBALANCE;
1349 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc1c][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XB_RX_IQ_IMBALANCE, MASKDWORD);
1350 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc78][KEY] = REG_OFDM_0_AGC_RSSI_TABLE;
1351 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc78][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_AGC_RSSI_TABLE, MASKDWORD);
1352 return;
1353 }
1354
1355 /* 2 Rx IQC */
1356 reg = result[final_candidate][6];
1357 odm_set_bb_reg(dm, REG_OFDM_0_XB_RX_IQ_IMBALANCE, 0x3FF, reg);
1358 reg = result[final_candidate][7] & 0x3F;
1359 odm_set_bb_reg(dm, REG_OFDM_0_XB_RX_IQ_IMBALANCE, 0xFC00, reg);
1360 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc1c][KEY] = REG_OFDM_0_XB_RX_IQ_IMBALANCE;
1361 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc1c][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_XB_RX_IQ_IMBALANCE, MASKDWORD);
1362
1363 reg = (result[final_candidate][7] >> 6) & 0xF;
1364 odm_set_bb_reg(dm, REG_OFDM_0_AGC_RSSI_TABLE, 0x0000F000, reg);
1365 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc78][KEY] = REG_OFDM_0_AGC_RSSI_TABLE;
1366 cali_info->rx_iqc_8723b[PATH_S0][idx_0xc78][VAL] = odm_get_bb_reg(dm, REG_OFDM_0_AGC_RSSI_TABLE, MASKDWORD);
1367 }
1368 }
1369 #endif
1370
_phy_save_adda_registers8188f(struct dm_struct * dm,u32 * adda_reg,u32 * adda_backup,u32 register_num)1371 void _phy_save_adda_registers8188f(struct dm_struct *dm, u32 *adda_reg,
1372 u32 *adda_backup, u32 register_num)
1373 {
1374 u32 i;
1375 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1376 if (odm_check_power_status(dm) == false)
1377 return;
1378 #endif
1379 RF_DBG(dm, DBG_RF_IQK, "Save ADDA parameters.\n");
1380 for (i = 0; i < register_num; i++)
1381 adda_backup[i] = odm_get_bb_reg(dm, adda_reg[i], MASKDWORD);
1382 }
1383
_phy_save_mac_registers8188f(struct dm_struct * dm,u32 * mac_reg,u32 * mac_backup)1384 void _phy_save_mac_registers8188f(struct dm_struct *dm, u32 *mac_reg,
1385 u32 *mac_backup)
1386 {
1387 u32 i;
1388 RF_DBG(dm, DBG_RF_IQK, "Save MAC parameters.\n");
1389 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1390 mac_backup[i] = odm_read_1byte(dm, mac_reg[i]);
1391 mac_backup[i] = odm_read_4byte(dm, mac_reg[i]);
1392 }
1393
_phy_reload_adda_registers8188f(struct dm_struct * dm,u32 * adda_reg,u32 * adda_backup,u32 regiester_num)1394 void _phy_reload_adda_registers8188f(struct dm_struct *dm, u32 *adda_reg,
1395 u32 *adda_backup, u32 regiester_num)
1396 {
1397 u32 i;
1398
1399 RF_DBG(dm, DBG_RF_IQK, "Reload ADDA power saving parameters !\n");
1400 for (i = 0; i < regiester_num; i++)
1401 odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, adda_backup[i]);
1402 }
1403
_phy_reload_mac_registers8188f(struct dm_struct * dm,u32 * mac_reg,u32 * mac_backup)1404 void _phy_reload_mac_registers8188f(struct dm_struct *dm, u32 *mac_reg,
1405 u32 *mac_backup)
1406 {
1407 u32 i;
1408 RF_DBG(dm, DBG_RF_IQK, "Reload MAC parameters !\n");
1409 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1410 odm_write_1byte(dm, mac_reg[i], (u8)mac_backup[i]);
1411 odm_write_4byte(dm, mac_reg[i], mac_backup[i]);
1412 }
1413
_phy_path_adda_on8188f(struct dm_struct * dm,u32 * adda_reg,boolean is_path_a_on,boolean is2T)1414 void _phy_path_adda_on8188f(struct dm_struct *dm, u32 *adda_reg,
1415 boolean is_path_a_on, boolean is2T)
1416 {
1417 u32 path_on;
1418 u32 i;
1419 RF_DBG(dm, DBG_RF_IQK, "ADDA ON.\n");
1420
1421 path_on = is_path_a_on ? 0x03c00014 : 0x03c00014;
1422 if (false == is2T) {
1423 path_on = 0x03c00014;
1424 odm_set_bb_reg(dm, adda_reg[0], MASKDWORD, 0x03c00014);
1425 } else
1426 odm_set_bb_reg(dm, adda_reg[0], MASKDWORD, path_on);
1427
1428 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1429 odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, path_on);
1430 }
1431
_phy_mac_setting_calibration8188f(struct dm_struct * dm,u32 * mac_reg,u32 * mac_backup)1432 void _phy_mac_setting_calibration8188f(struct dm_struct *dm, u32 *mac_reg,
1433 u32 *mac_backup)
1434 {
1435 //u32 i = 0;
1436 RF_DBG(dm, DBG_RF_IQK, "MAC settings for Calibration.\n");
1437
1438 #if 0
1439 odm_write_1byte(dm, mac_reg[i], 0x3F);
1440
1441 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1442 odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(3))));
1443 odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(5))));
1444 #else
1445
1446 odm_set_bb_reg(dm, R_0x520, 0x00ff0000, 0xff);
1447 #endif
1448 }
1449
_phy_path_a_stand_by8188f(struct dm_struct * dm)1450 void _phy_path_a_stand_by8188f(struct dm_struct *dm)
1451 {
1452 RF_DBG(dm, DBG_RF_IQK, "path-A standby mode!\n");
1453
1454 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
1455 /* Allen */
1456 odm_set_rf_reg(dm, RF_PATH_A, RF_AC, MASKDWORD, 0x10000);
1457 /* odm_set_bb_reg(dm, R_0x840, MASKDWORD, 0x00010000);
1458 * */
1459 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000);
1460 }
1461
_phy_pi_mode_switch8188f(struct dm_struct * dm,boolean pi_mode)1462 void _phy_pi_mode_switch8188f(struct dm_struct *dm, boolean pi_mode)
1463 {
1464 u32 mode;
1465 RF_DBG(dm, DBG_RF_IQK, "BB Switch to %s mode!\n",
1466 (pi_mode ? "PI" : "SI"));
1467
1468 mode = pi_mode ? 0x01000100 : 0x01000000;
1469 odm_set_bb_reg(dm, REG_FPGA0_XA_HSSI_PARAMETER1, MASKDWORD, mode);
1470 odm_set_bb_reg(dm, REG_FPGA0_XB_HSSI_PARAMETER1, MASKDWORD, mode);
1471 }
1472
1473 boolean
phy_simularity_compare_8188f(struct dm_struct * dm,s32 result[][8],u8 c1,u8 c2,boolean is2t)1474 phy_simularity_compare_8188f(struct dm_struct *dm, s32 result[][8], u8 c1,
1475 u8 c2, boolean is2t)
1476 {
1477 u32 i, j, diff, simularity_bit_map, bound = 0;
1478 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
1479 boolean is_result = true;
1480 /* #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
1481 /* bool is2T = IS_92C_SERIAL( hal_data->version_id);
1482 * #else */
1483 /* #endif */
1484
1485 s32 tmp1 = 0, tmp2 = 0;
1486
1487 if (is2t)
1488 bound = 8;
1489 else
1490 bound = 4;
1491
1492 RF_DBG(dm, DBG_RF_IQK,
1493 "===> IQK:phy_simularity_compare_8192e c1 %d c2 %d!!!\n", c1,
1494 c2);
1495
1496 simularity_bit_map = 0;
1497
1498 for (i = 0; i < bound; i++) {
1499 if (i == 1 || i == 3 || i == 5 || i == 7) {
1500 if ((result[c1][i] & 0x00000200) != 0)
1501 tmp1 = result[c1][i] | 0xFFFFFC00;
1502 else
1503 tmp1 = result[c1][i];
1504
1505 if ((result[c2][i] & 0x00000200) != 0)
1506 tmp2 = result[c2][i] | 0xFFFFFC00;
1507 else
1508 tmp2 = result[c2][i];
1509 } else {
1510 tmp1 = result[c1][i];
1511 tmp2 = result[c2][i];
1512 }
1513
1514 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1515
1516 if (diff > MAX_TOLERANCE) {
1517 RF_DBG(dm, DBG_RF_IQK,
1518 "IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n",
1519 diff, i, result[c1][i], result[c2][i]);
1520
1521 if ((i == 2 || i == 6) && !simularity_bit_map) {
1522 if (result[c1][i] + result[c1][i + 1] == 0)
1523 final_candidate[(i / 4)] = c2;
1524 else if (result[c2][i] + result[c2][i + 1] == 0)
1525 final_candidate[(i / 4)] = c1;
1526 else
1527 simularity_bit_map = simularity_bit_map | (1 << i);
1528 } else
1529 simularity_bit_map = simularity_bit_map | (1 << i);
1530 }
1531 }
1532
1533 RF_DBG(dm, DBG_RF_IQK,
1534 "IQK:phy_simularity_compare_8192e simularity_bit_map %x !!!\n",
1535 simularity_bit_map);
1536
1537 if (simularity_bit_map == 0) {
1538 for (i = 0; i < (bound / 4); i++) {
1539 if (final_candidate[i] != 0xFF) {
1540 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1541 result[3][j] = result[final_candidate[i]][j];
1542 is_result = false;
1543 }
1544 }
1545 return is_result;
1546 }
1547
1548 if (!(simularity_bit_map & 0x03)) { /* path A TX OK */
1549 for (i = 0; i < 2; i++)
1550 result[3][i] = result[c1][i];
1551 }
1552
1553 if (!(simularity_bit_map & 0x0c)) { /* path A RX OK */
1554 for (i = 2; i < 4; i++)
1555 result[3][i] = result[c1][i];
1556 }
1557
1558 if (!(simularity_bit_map & 0x30)) { /* path B TX OK */
1559 for (i = 4; i < 6; i++)
1560 result[3][i] = result[c1][i];
1561 }
1562
1563 if (!(simularity_bit_map & 0xc0)) { /* path B RX OK */
1564 for (i = 6; i < 8; i++)
1565 result[3][i] = result[c1][i];
1566 }
1567 return false;
1568 }
1569
_phy_iq_calibrate_8188f(struct dm_struct * dm,s32 result[][8],u8 t,boolean is2T)1570 void _phy_iq_calibrate_8188f(struct dm_struct *dm, s32 result[][8], u8 t,
1571 boolean is2T)
1572 {
1573 u32 i;
1574 u8 path_aok = 0x0; //, path_bok = 0x0;
1575 u8 tmp0xc50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
1576 u8 tmp0xc58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
1577 u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
1578 REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
1579 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1580 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1581 REG_TX_OFDM_BBON, REG_TX_TO_RX,
1582 REG_TX_TO_TX, REG_RX_CCK,
1583 REG_RX_OFDM, REG_RX_WAIT_RIFS,
1584 REG_RX_TO_RX, REG_STANDBY,
1585 REG_SLEEP, REG_PMPD_ANAEN};
1586 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1587 REG_TXPAUSE, REG_BCN_CTRL,
1588 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
1589
1590 /* since 92C & 92D have the different define in IQK_BB_REG */
1591 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1592 REG_OFDM_0_TRX_PATH_ENABLE, REG_OFDM_0_TR_MUX_PAR,
1593 REG_FPGA0_XCD_RF_INTERFACE_SW, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1594 REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
1595 REG_FPGA0_XB_RF_INTERFACE_OE, REG_FPGA0_RFMOD};
1596
1597 //u32 path_sel_bb;
1598 u32 path_sel_rf;
1599 u32 retry_count;
1600
1601 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1602 retry_count = 2;
1603 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1604 #if MP_DRIVER
1605 retry_count = 9;
1606 #else
1607 retry_count = 2;
1608 #endif
1609 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1610 if (*(dm->mp_mode))
1611 retry_count = 9;
1612 else
1613 retry_count = 2;
1614 #endif
1615
1616 /* Note: IQ calibration must be performed after loading */
1617 /* PHY_REG.txt , and radio_a, radio_b.txt */
1618
1619 /* u32 bbvalue; */
1620
1621 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1622 #ifdef MP_TEST
1623 if (*(dm->mp_mode))
1624 retry_count = 9;
1625 #endif
1626 #endif
1627
1628 if (t == 0) {
1629 /* bbvalue = odm_get_bb_reg(dm, REG_FPGA0_RFMOD, MASKDWORD);
1630 * RT_DISP(FINIT, INIT_IQK, ("_phy_iq_calibrate_8188f()==>0x%08x\n",bbvalue)); */
1631
1632 RF_DBG(dm, DBG_RF_IQK, "IQ Calibration for %s for %d times\n",
1633 (is2T ? "2T2R" : "1T1R"), t);
1634
1635 /* Save ADDA parameters, turn path A ADDA on */
1636 _phy_save_adda_registers8188f(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1637 _phy_save_mac_registers8188f(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
1638 _phy_save_adda_registers8188f(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1639 }
1640 RF_DBG(dm, DBG_RF_IQK, "IQ Calibration for %s for %d times\n",
1641 (is2T ? "2T2R" : "1T1R"), t);
1642 _phy_path_adda_on8188f(dm, ADDA_REG, true, is2T);
1643
1644 if (t == 0)
1645 dm->rf_calibrate_info.is_rf_pi_enable = (u8)odm_get_bb_reg(dm, REG_FPGA0_XA_HSSI_PARAMETER1, BIT(8));
1646
1647 #if 0
1648 if (!dm->rf_calibrate_info.is_rf_pi_enable) {
1649 /* Switch BB to PI mode to do IQ Calibration. */
1650 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1651 _phy_pi_mode_switch8188f(adapter, true);
1652 #else
1653 _phy_pi_mode_switch8188f(dm, true);
1654 #endif
1655 }
1656 #endif
1657
1658 /* save RF path */
1659 // path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
1660 // path_sel_rf = odm_get_rf_reg(dm, RF_PATH_A, RF_0xb0, 0xfffff);
1661
1662 /* BB setting */
1663 /*odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT24, 0x00);*/
1664 odm_set_bb_reg(dm, REG_OFDM_0_TRX_PATH_ENABLE, MASKDWORD, 0x03a05600);
1665 odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800e4);
1666 odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x25204000);
1667
1668 /* external switch control
1669 * odm_set_bb_reg(dm, REG_FPGA0_XAB_RF_INTERFACE_SW, BIT(10), 0x01);
1670 * odm_set_bb_reg(dm, REG_FPGA0_XAB_RF_INTERFACE_SW, BIT(26), 0x01);
1671 * odm_set_bb_reg(dm, REG_FPGA0_XA_RF_INTERFACE_OE, BIT(10), 0x00);
1672 * odm_set_bb_reg(dm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(10), 0x00); */
1673
1674 if (is2T) {
1675 /* Allen */
1676 /* odm_set_bb_reg(dm, REG_FPGA0_XA_LSSI_PARAMETER, MASKDWORD, 0x00010000); */
1677 /* odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_PARAMETER, MASKDWORD, 0x00010000); */
1678 odm_set_rf_reg(dm, RF_PATH_B, RF_AC, MASKDWORD, 0x10000);
1679 }
1680
1681 /* MAC settings */
1682 _phy_mac_setting_calibration8188f(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
1683
1684 /* Page B init */
1685 /* AP or IQK
1686 * odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000); */
1687
1688 if (is2T) {
1689 /* odm_set_bb_reg(dm, REG_CONFIG_ANT_B, MASKDWORD, 0x0f600000); */
1690 }
1691
1692 /* IQ calibration setting */
1693 RF_DBG(dm, DBG_RF_IQK, "IQK setting!\n");
1694 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000);
1695 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
1696 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
1697
1698 for (i = 0; i < retry_count; i++) {
1699 path_aok = phy_path_a_iqk_8188f(dm, is2T);
1700 /* if(path_aok == 0x03){ */
1701 if (path_aok == 0x01) { /* path A Tx IQK Success */
1702 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
1703 dm->rf_calibrate_info.tx_lok[RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK);
1704
1705 RF_DBG(dm, DBG_RF_IQK, "path A Tx IQK Success!!\n");
1706 result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1707 result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1708 break;
1709 }
1710 #if 0
1711 else if (i == (retry_count - 1) && path_aok == 0x01) { /* Tx IQK OK */
1712 RT_DISP(FINIT, INIT_IQK, ("path A IQK Only Tx Success!!\n"));
1713
1714 result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1715 result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1716 }
1717 #endif
1718 }
1719
1720 /* bypass RXQIK */
1721 #if 1
1722
1723 for (i = 0; i < retry_count; i++) {
1724 path_aok = phy_path_a_rx_iqk_8188f(dm, is2T);
1725 if (path_aok == 0x03) {
1726 RF_DBG(dm, DBG_RF_IQK, "path A Rx IQK Success!!\n");
1727 /* result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
1728 * result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
1729 result[t][2] = (odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1730 result[t][3] = (odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1731 break;
1732 }
1733
1734 RF_DBG(dm, DBG_RF_IQK, "path A Rx IQK Fail!!\n");
1735 }
1736 #endif
1737
1738 if (path_aok == 0x0)
1739 RF_DBG(dm, DBG_RF_IQK, "path A IQK failed!!\n");
1740 #if 0
1741 if (is2T) {
1742 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1743 _phy_path_a_stand_by8188f(adapter);
1744
1745 /* Turn path B ADDA on */
1746 _phy_path_adda_on8188f(adapter, ADDA_REG, false, is2T);
1747 #else
1748 _phy_path_a_stand_by8188f(dm);
1749
1750 /* Turn path B ADDA on */
1751 _phy_path_adda_on8188f(dm, ADDA_REG, false, is2T);
1752 #endif
1753 /* Allen */
1754 for (i = 0; i < retry_count; i++) {
1755 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1756 path_bok = phy_path_b_iqk_8188f(adapter);
1757 #else
1758 path_bok = phy_path_b_iqk_8188f(dm);
1759 #endif
1760 /* if(path_bok == 0x03){ */
1761 if (path_bok == 0x01) { /* path B Tx IQK Success */
1762 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
1763 dm->rf_calibrate_info.tx_lok[RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B, RF_0x8, RFREGOFFSETMASK);
1764
1765 RF_DBG(dm, DBG_RF_IQK,
1766 "path B Tx IQK Success!!\n");
1767 result[t][4] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1768 result[t][5] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1769 break;
1770 }
1771 #if 0
1772 else if (i == (retry_count - 1) && path_aok == 0x01) { /* Tx IQK OK */
1773 RT_DISP(FINIT, INIT_IQK, ("path B IQK Only Tx Success!!\n"));
1774
1775 result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
1776 result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
1777 }
1778 #endif
1779 }
1780
1781 /* bypass RXQIK */
1782 #if 0
1783
1784 for (i = 0; i < retry_count; i++) {
1785 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1786 path_bok = phy_path_b_rx_iqk_8188f(adapter, is2T);
1787 #else
1788 path_bok = phy_path_b_rx_iqk_8188f(dm, is2T);
1789 #endif
1790 if (path_bok == 0x03) {
1791 RF_DBG(dm, DBG_RF_IQK,
1792 "path B Rx IQK Success!!\n");
1793 /* result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
1794 * result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
1795 result[t][6] = (odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_B_2, MASKDWORD) & 0x3FF0000) >> 16;
1796 result[t][7] = (odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_B_2, MASKDWORD) & 0x3FF0000) >> 16;
1797 break;
1798 }
1799
1800 RF_DBG(dm, DBG_RF_IQK, "path B Rx IQK Fail!!\n");
1801 }
1802 #endif
1803
1804 /* ======Allen end ========= */
1805 if (0x00 == path_bok)
1806 RF_DBG(dm, DBG_RF_IQK, "path B IQK failed!!\n");
1807 }
1808 #endif
1809 /* Back to BB mode, load original value */
1810 RF_DBG(dm, DBG_RF_IQK, "IQK:Back to BB mode, load original value!\n");
1811 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0);
1812
1813 if (t != 0) {
1814 if (!dm->rf_calibrate_info.is_rf_pi_enable) {
1815 /* Switch back BB to SI mode after finish IQ Calibration. */
1816 _phy_pi_mode_switch8188f(dm, false);
1817 }
1818 /* Reload ADDA power saving parameters */
1819 _phy_reload_adda_registers8188f(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1820 /* Reload MAC parameters */
1821 _phy_reload_mac_registers8188f(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
1822 _phy_reload_adda_registers8188f(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1823 /* Reload RF path */
1824 // odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
1825 // odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, 0xfffff, path_sel_rf);
1826
1827 /* Allen initial gain 0xc50 */
1828 /* Restore RX initial gain */
1829 odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, 0x50);
1830 odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, tmp0xc50);
1831 if (is2T) {
1832 odm_set_bb_reg(dm, R_0xc58, MASKBYTE0, 0x50);
1833 odm_set_bb_reg(dm, R_0xc58, MASKBYTE0, tmp0xc58);
1834 }
1835
1836 /* load 0xe30 IQC default value */
1837 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1838 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1839 }
1840 RF_DBG(dm, DBG_RF_IQK, "%s <==\n", __func__);
1841 }
1842
_phy_lc_calibrate_8188f(struct dm_struct * dm,boolean is2T)1843 void _phy_lc_calibrate_8188f(struct dm_struct *dm, boolean is2T)
1844 {
1845 u8 tmp_reg;
1846 u32 rf_bmode = 0, lc_cal, cnt;
1847
1848 /*Check continuous TX and Packet TX*/
1849 tmp_reg = odm_read_1byte(dm, 0xd03);
1850
1851 if ((tmp_reg & 0x70) != 0) /*Deal with contisuous TX case*/
1852 odm_write_1byte(dm, 0xd03, tmp_reg & 0x8F); /*disable all continuous TX*/
1853 else /* Deal with Packet TX case*/
1854 odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* block all queues*/
1855
1856 /*backup RF0x18*/
1857 lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
1858
1859 /*Start LCK*/
1860 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
1861
1862 for (cnt = 0; cnt < 100; cnt++) {
1863 if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
1864 break;
1865 ODM_delay_ms(10);
1866 }
1867
1868 if (cnt == 100)
1869 RF_DBG(dm, DBG_RF_LCK, "LCK time out\n");
1870
1871 /*Recover channel number*/
1872 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
1873
1874 /*Restore original situation*/
1875 if ((tmp_reg & 0x70) != 0) {
1876 /*Deal with contisuous TX case*/
1877 odm_write_1byte(dm, 0xd03, tmp_reg);
1878 } else {
1879 /* Deal with Packet TX case*/
1880 odm_write_1byte(dm, REG_TXPAUSE, 0x00);
1881 }
1882 }
1883
phy_iq_calibrate_8188f(void * dm_void,boolean is_recovery)1884 void phy_iq_calibrate_8188f(void *dm_void, boolean is_recovery)
1885 {
1886 struct dm_struct *dm = (struct dm_struct *)dm_void;
1887 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1888 s32 result[4][8]; /* last is final result */
1889 u8 i, final_candidate, indexforchannel;
1890 boolean is_patha_ok, is_pathb_ok;
1891 #if 1 //DBG
1892 s32 rege94, rege9c, regea4, regeac, regeb4 = 0, regebc = 0, regec4 = 0, regecc = 0, reg_tmp = 0;
1893 #else
1894 s32 rege94, regea4, regeb4, regec4, reg_tmp = 0;
1895 #endif
1896 boolean is12simular, is13simular, is23simular;
1897 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1898 REG_OFDM_0_XA_RX_IQ_IMBALANCE, REG_OFDM_0_XB_RX_IQ_IMBALANCE,
1899 REG_OFDM_0_ECCA_THRESHOLD, REG_OFDM_0_AGC_RSSI_TABLE,
1900 REG_OFDM_0_XA_TX_IQ_IMBALANCE, REG_OFDM_0_XB_TX_IQ_IMBALANCE,
1901 REG_OFDM_0_XC_TX_AFE, REG_OFDM_0_XD_TX_AFE,
1902 REG_OFDM_0_RX_IQ_EXT_ANTA};
1903 //u32 path_sel_bb = 0;
1904 u32 path_sel_rf = 0;
1905
1906 #if 0
1907 if (is_restore) {
1908 u32 offset, data;
1909 u8 path, is_result = SUCCESS;
1910 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
1911
1912 /* #define PATH_S0 1 */ /* RF_PATH_B */
1913 /* #define PATH_S1 0 */ /* RF_PATH_A */
1914
1915 path = (odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKBYTE0) == 0x00) ? RF_PATH_A : RF_PATH_B;
1916 /* Restore TX IQK */
1917 for (i = 0; i < 3; ++i) {
1918 offset = cali_info->tx_iqc_8723b[path][i][0];
1919 data = cali_info->tx_iqc_8723b[path][i][1];
1920 if (offset == 0 || data == 0) {
1921 is_result = FAIL;
1922 break;
1923 }
1924 RT_TRACE(COMP_MP, DBG_TRACE, ("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data));
1925 odm_set_bb_reg(dm, offset, MASKDWORD, data);
1926 }
1927 /* Restore RX IQK */
1928 for (i = 0; i < 2; ++i) {
1929 offset = cali_info->rx_iqc_8723b[path][i][0];
1930 data = cali_info->rx_iqc_8723b[path][i][1];
1931 if (offset == 0 || data == 0) {
1932 is_result = FAIL;
1933 break;
1934 }
1935 RT_TRACE(COMP_MP, DBG_TRACE, ("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data));
1936 odm_set_bb_reg(dm, offset, MASKDWORD, data);
1937 }
1938
1939 if (dm->rf_calibrate_info.tx_lok[RF_PATH_A] == 0)
1940 is_result = FAIL;
1941 else {
1942 odm_set_rf_reg(dm, RF_PATH_A, RF_TXM_IDAC, RFREGOFFSETMASK, dm->rf_calibrate_info.tx_lok[RF_PATH_A]);
1943 odm_set_rf_reg(dm, RF_PATH_B, RF_TXM_IDAC, RFREGOFFSETMASK, dm->rf_calibrate_info.tx_lok[RF_PATH_B]);
1944 }
1945
1946 if (is_result == SUCCESS)
1947 return;
1948 }
1949 #endif
1950
1951 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
1952 if (is_recovery)
1953 #else /* for ODM_WIN */
1954 if (is_recovery && !dm->is_in_hct_test) /* YJ,add for PowerTest,120405 */
1955 #endif
1956 {
1957 RF_DBG(dm, DBG_RF_INIT, "%s: Return due to is_recovery!\n",
1958 __func__);
1959 _phy_reload_adda_registers8188f(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, 9);
1960 return;
1961 }
1962 RF_DBG(dm, DBG_RF_IQK, "IQK:Start!!!\n");
1963
1964 /* Save RF path */
1965 // path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
1966 // path_sel_rf = odm_get_rf_reg(dm, RF_PATH_A, RF_0xb0, 0xfffff);
1967
1968 for (i = 0; i < 8; i++) {
1969 result[0][i] = 0;
1970 result[1][i] = 0;
1971 result[2][i] = 0;
1972 result[3][i] = 0;
1973 }
1974 final_candidate = 0xff;
1975 is_patha_ok = false;
1976 is_pathb_ok = false;
1977 is12simular = false;
1978 is23simular = false;
1979 is13simular = false;
1980
1981 for (i = 0; i < 3; i++) {
1982 _phy_iq_calibrate_8188f(dm, result, i, false);
1983
1984 if (i == 1) {
1985 is12simular = phy_simularity_compare_8188f(dm, result, 0, 1, true);
1986 if (is12simular) {
1987 final_candidate = 0;
1988 RF_DBG(dm, DBG_RF_IQK,
1989 "IQK: is12simular final_candidate is %x\n",
1990 final_candidate);
1991 break;
1992 }
1993 }
1994
1995 if (i == 2) {
1996 is13simular = phy_simularity_compare_8188f(dm, result, 0, 2, true);
1997 if (is13simular) {
1998 final_candidate = 0;
1999 RF_DBG(dm, DBG_RF_IQK,
2000 "IQK: is13simular final_candidate is %x\n",
2001 final_candidate);
2002
2003 break;
2004 }
2005
2006 is23simular = phy_simularity_compare_8188f(dm, result, 1, 2, true);
2007
2008 if (is23simular) {
2009 final_candidate = 1;
2010 RF_DBG(dm, DBG_RF_IQK,
2011 "IQK: is23simular final_candidate is %x\n",
2012 final_candidate);
2013 } else {
2014 for (i = 0; i < 8; i++)
2015 reg_tmp += result[3][i];
2016
2017 if (reg_tmp != 0)
2018 final_candidate = 3;
2019 else
2020 final_candidate = 0xFF;
2021 }
2022 }
2023 }
2024 /* RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n")); */
2025
2026 for (i = 0; i < 4; i++) {
2027 rege94 = result[i][0];
2028 regea4 = result[i][2];
2029 regeb4 = result[i][4];
2030 regec4 = result[i][6];
2031 #if DBG
2032 rege9c = result[i][1];
2033 regeac = result[i][3];
2034 regebc = result[i][5];
2035 regecc = result[i][7];
2036 #endif
2037 //RF_DBG(dm, DBG_RF_IQK, "IQK: rege94=%04x rege9c=%04x regea4=%04x regeac=%04x regeb4=%04x regebc=%04x regec4=%04x regecc=%04x\n",
2038 // rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc);
2039 }
2040
2041 if (final_candidate != 0xff) {
2042 dm->rf_calibrate_info.rege94 = result[final_candidate][0];
2043 dm->rf_calibrate_info.rege9c = result[final_candidate][1];
2044 dm->rf_calibrate_info.regeb4 = result[final_candidate][4];
2045 dm->rf_calibrate_info.regebc = result[final_candidate][5];
2046
2047 rege94 = result[final_candidate][0];
2048 regea4 = result[final_candidate][2];
2049 regeb4 = result[final_candidate][4];
2050 regec4 = result[final_candidate][6];
2051 #if DBG
2052 rege9c = result[final_candidate][1];
2053 regeac = result[final_candidate][3];
2054 regebc = result[final_candidate][5];
2055 regecc = result[final_candidate][7];
2056 #endif
2057 RF_DBG(dm, DBG_RF_IQK, "IQK: final_candidate is %x\n",
2058 final_candidate);
2059 //RF_DBG(dm, DBG_RF_IQK, "IQK: rege94=%04x rege9c=%04x regea4=%04x regeac=%04x regeb4=%04x regebc=%04x regec4=%04x regecc=%04x\n",
2060 // rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc);
2061 is_patha_ok = is_pathb_ok = true;
2062 } else {
2063 RF_DBG(dm, DBG_RF_IQK, "IQK: FAIL use default value\n");
2064
2065 dm->rf_calibrate_info.rege94 = dm->rf_calibrate_info.regeb4 = 0x100; /* X default value */
2066 dm->rf_calibrate_info.rege9c = dm->rf_calibrate_info.regebc = 0x0; /* Y default value */
2067 }
2068
2069 if (rege94 != 0)
2070 _phy_path_a_fill_iqk_matrix8188f(dm, is_patha_ok, result, final_candidate, (regea4 == 0));
2071
2072 #if 0
2073 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2074 #if MP_DRIVER == 1
2075 if (rf_path == RF_PATH_A || ((*dm->mp_mode) == 0))
2076 #endif
2077 {
2078 if (regeb4 != 0)
2079 _phy_path_b_fill_iqk_matrix8188f(dm, is_pathb_ok, result, final_candidate, (regec4 == 0));
2080 }
2081 #endif
2082 #endif
2083
2084 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2085 indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
2086 #else
2087 indexforchannel = 0;
2088 #endif
2089
2090 /* To Fix BSOD when final_candidate is 0xff
2091 * by sherry 20120321 */
2092 if (final_candidate < 4) {
2093 for (i = 0; i < iqk_matrix_reg_num; i++)
2094 dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].value[0][i] = result[final_candidate][i];
2095 dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].is_iqk_done = true;
2096 }
2097 /* RT_DISP(FINIT, INIT_IQK, ("\nIQK OK indexforchannel %d.\n", indexforchannel)); */
2098 RF_DBG(dm, DBG_RF_IQK, "\nIQK OK indexforchannel %d.\n",
2099 indexforchannel);
2100 _phy_save_adda_registers8188f(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
2101
2102 /* Restore RF path */
2103 // odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
2104 // odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, 0xfffff, path_sel_rf);
2105
2106 RF_DBG(dm, DBG_RF_IQK, "IQK finished 8188F\n");
2107 }
2108
phy_lc_calibrate_8188f(void * dm_void)2109 void phy_lc_calibrate_8188f(void *dm_void)
2110 {
2111 struct dm_struct *dm = (struct dm_struct *)dm_void;
2112
2113 _phy_lc_calibrate_8188f(dm, false);
2114 }
2115
_phy_set_rf_path_switch_8188f(struct dm_struct * dm,boolean is_main,boolean is2T)2116 void _phy_set_rf_path_switch_8188f(
2117 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
2118 struct dm_struct *dm,
2119 #else
2120 void *adapter,
2121 #endif
2122 boolean is_main, boolean is2T)
2123 {
2124 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2125 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2126 struct dm_struct *dm = &hal_data->DM_OutSrc;
2127 #endif
2128
2129 if (is_main) /* Left antenna */
2130 odm_set_bb_reg(dm, R_0x92c, MASKDWORD, 0x1);
2131 else
2132 odm_set_bb_reg(dm, R_0x92c, MASKDWORD, 0x2);
2133 }
2134
phy_set_rf_path_switch_8188f(struct dm_struct * dm,boolean is_main)2135 void phy_set_rf_path_switch_8188f(
2136 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
2137 struct dm_struct *dm,
2138 #else
2139 void *adapter,
2140 #endif
2141 boolean is_main)
2142 {
2143 #if DISABLE_BB_RF
2144 return;
2145 #endif
2146
2147 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2148 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2149 _phy_set_rf_path_switch_8188f(dm, is_main, true);
2150 #else
2151 _phy_set_rf_path_switch_8188f(adapter, is_main, true);
2152 #endif
2153 #endif
2154 }
2155
2156 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2157 /* return value true => Main; false => Aux */
2158
_phy_query_rf_path_switch_8188f(struct dm_struct * dm,boolean is2T)2159 boolean _phy_query_rf_path_switch_8188f(
2160 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2161 struct dm_struct *dm,
2162 #else
2163 void *adapter,
2164 #endif
2165 boolean is2T)
2166 {
2167 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2168 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2169 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2170 struct dm_struct *dm = &hal_data->odmpriv;
2171 #endif
2172 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2173 struct dm_struct *dm = &hal_data->DM_OutSrc;
2174 #endif
2175 #endif
2176
2177 if (odm_get_bb_reg(dm, R_0x92c, MASKDWORD) == 0x01)
2178 return true;
2179 else
2180 return false;
2181 }
2182
2183 /* return value true => Main; false => Aux */
phy_query_rf_path_switch_8188f(struct dm_struct * dm)2184 boolean phy_query_rf_path_switch_8188f(
2185 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2186 struct dm_struct *dm
2187 #else
2188 void *adapter
2189 #endif
2190 )
2191 {
2192 #if DISABLE_BB_RF
2193 return true;
2194 #endif
2195
2196 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2197 return _phy_query_rf_path_switch_8188f(adapter, false);
2198 #else
2199 return _phy_query_rf_path_switch_8188f(dm, false);
2200 #endif
2201 }
2202 #endif
2203
phy_psd_log2base(u32 val)2204 u32 phy_psd_log2base(u32 val)
2205 {
2206 u8 i, j;
2207 u32 tmp, tmp2, val_integerdb = 0, tindex, shiftcount = 0;
2208 u32 result, val_fractiondb = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
2209 174, 151, 132, 115, 100, 86,
2210 74, 62, 51, 42, 32, 23, 15, 7, 0};
2211
2212 if (val == 0)
2213 return 0;
2214
2215 tmp = val;
2216 while (1) {
2217 if (tmp == 1)
2218 break;
2219
2220 else {
2221 tmp = (tmp >> 1);
2222 shiftcount++;
2223 }
2224 }
2225
2226 val_integerdb = shiftcount + 1;
2227 tmp2 = 1;
2228
2229 for (j = 1; j <= val_integerdb; j++)
2230 tmp2 = tmp2 * 2;
2231
2232 tmp = (val * 100) / tmp2;
2233 tindex = tmp / 5;
2234
2235 if (tindex > 20)
2236 tindex = 20;
2237
2238 val_fractiondb = table_fraction[tindex];
2239
2240 result = val_integerdb * 100 - val_fractiondb;
2241
2242 return result;
2243 }
2244
phy_active_large_power_detection_8188f(struct dm_struct * dm)2245 void phy_active_large_power_detection_8188f(struct dm_struct *dm)
2246 {
2247 u8 i = 1, j = 0, retrycnt = 2;
2248 u32 threshold_psd = 56, tmp_psd = 0, tmp_psd_db = 0, rf_mode;
2249
2250 u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
2251 REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
2252 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
2253 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
2254 REG_TX_OFDM_BBON, REG_TX_TO_RX,
2255 REG_TX_TO_TX, REG_RX_CCK,
2256 REG_RX_OFDM, REG_RX_WAIT_RIFS,
2257 REG_RX_TO_RX, REG_STANDBY,
2258 REG_SLEEP, REG_PMPD_ANAEN};
2259 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
2260 REG_TXPAUSE, REG_BCN_CTRL,
2261 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
2262
2263 /* since 92C & 92D have the different define in IQK_BB_REG */
2264 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
2265 REG_OFDM_0_TRX_PATH_ENABLE, REG_OFDM_0_TR_MUX_PAR,
2266 REG_FPGA0_XCD_RF_INTERFACE_SW, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
2267 REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
2268 REG_FPGA0_XB_RF_INTERFACE_OE, REG_FPGA0_RFMOD};
2269
2270 BOOLEAN goout = FALSE;
2271
2272 _phy_save_adda_registers8188f(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
2273 _phy_save_mac_registers8188f(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
2274 _phy_save_adda_registers8188f(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
2275
2276 _phy_path_adda_on8188f(dm, ADDA_REG, TRUE, FALSE);
2277
2278 rf_mode = odm_get_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK);
2279 /*RF_DBG(dm, DBG_RF_IQK, "[Act_Large_PWR]Original RF mode = 0x%x\n", odm_get_rf_reg(dm, ODM_RF_PATH_A, RF_0x0, RFREGOFFSETMASK));*/
2280
2281 do {
2282 switch (i) {
2283 case 1: /*initial setting*/
2284 RF_DBG(dm, DBG_RF_IQK,
2285 "[Act_Large_PWR]Loopback test Start!!\n");
2286 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
2287 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
2288 odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x28000);
2289 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x0000f);
2290 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0x3fffe);
2291 odm_set_rf_reg(dm, RF_PATH_A, RF_DBG_LP_RX2, 0x00800, 0x1);
2292 odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x00fff, 0x67);
2293
2294 odm_set_bb_reg(dm, REG_OFDM_0_TRX_PATH_ENABLE, MASKDWORD, 0x03a05600);
2295 odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800e4);
2296 odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x25204000);
2297
2298 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x808000);
2299 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x80007C00); /*set two tone*/
2300 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
2301 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
2302 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10009c1c);
2303 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82160000);
2304 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x2815200f);
2305 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a910);
2306
2307 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
2308 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
2309 ODM_delay_ms(IQK_DELAY_TIME_8188F);
2310
2311 if (odm_get_bb_reg(dm, R_0xea0, MASKDWORD) <= 0xa) {
2312 RF_DBG(dm, DBG_RF_IQK,
2313 "[Act_Large_PWR]Skip Activation due to abnormal 0xea0 value (0x%x)\n",
2314 odm_get_bb_reg(dm, R_0xea0, MASKDWORD));
2315 goout = TRUE;
2316 break;
2317
2318 } else {
2319 tmp_psd = 3 * (phy_psd_log2base(odm_get_bb_reg(dm, R_0xea0, MASKDWORD)));
2320 tmp_psd_db = tmp_psd / 100;
2321
2322 RF_DBG(dm, DBG_RF_IQK,
2323 "[Act_Large_PWR]0xea0 = 0x%x, tmp_PSD_dB = %d, (criterion = %d)\n",
2324 odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
2325 tmp_psd_db, threshold_psd);
2326
2327 i = 2;
2328 break;
2329 }
2330
2331 case 2: /*check PSD*/
2332 if (tmp_psd_db < threshold_psd) {
2333 if (j < retrycnt) {
2334 RF_DBG(dm, DBG_RF_IQK, "[Act_Large_PWR]Activation Start!!\n");
2335 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
2336 odm_set_bb_reg(dm, R_0x88c, BIT(20) | BIT(21), 0x3);
2337 odm_set_rf_reg(dm, RF_PATH_A, RF_0x58, 0x2, 0x1);
2338 /*RF_DBG(dm, DBG_RF_IQK, "[Act_Large_PWR]RF mode before set = %x\n", odm_get_rf_reg(dm, ODM_RF_PATH_A, RF_0x0, RFREGOFFSETMASK));*/
2339 odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, 0xf001f, 0x2001f);
2340 RF_DBG(dm, DBG_RF_IQK, "[Act_Large_PWR]set RF 0x0 = %x\n", odm_get_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK));
2341 ODM_delay_ms(200);
2342 odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, rf_mode);
2343 odm_set_rf_reg(dm, RF_PATH_A, RF_0x58, 0x2, 0x0);
2344 odm_set_bb_reg(dm, R_0x88c, BIT(20) | BIT(21), 0x0);
2345 ODM_delay_ms(100);
2346 i = 1;
2347 j++;
2348 break;
2349
2350 } else {
2351 RF_DBG(dm, DBG_RF_IQK, "[Act_Large_PWR]Activation fail!!!\n");
2352 goout = TRUE;
2353 break;
2354 }
2355 } else {
2356 RF_DBG(dm, DBG_RF_IQK,
2357 "[Act_Large_PWR]No need Activation!!!\n");
2358 goout = TRUE;
2359 break;
2360 }
2361 }
2362 } while (!goout);
2363
2364 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007C00);
2365 odm_set_bb_reg(dm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
2366 odm_set_rf_reg(dm, RF_PATH_A, RF_DBG_LP_RX2, 0x00800, 0x0);
2367 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);
2368 odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, rf_mode);
2369 RF_DBG(dm, DBG_RF_IQK, "[Act_Large_PWR]Reload RF mode = 0x%x\n",
2370 odm_get_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK));
2371
2372 _phy_reload_adda_registers8188f(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
2373 _phy_reload_mac_registers8188f(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
2374 _phy_reload_adda_registers8188f(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
2375
2376 RF_DBG(dm, DBG_RF_IQK, "[Act_Large_PWR]Activation process finish!!!\n");
2377 }
2378 #endif
2379