1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __HAL_PHY_REG_H__ 16*4882a593Smuzhiyun #define __HAL_PHY_REG_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* for PutRFRegsetting & GetRFRegSetting BitMask*/ 19*4882a593Smuzhiyun #define bRFRegOffsetMask 0xfffff 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* alias for phydm coding style */ 22*4882a593Smuzhiyun #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 23*4882a593Smuzhiyun #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 24*4882a593Smuzhiyun #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 25*4882a593Smuzhiyun #define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage 26*4882a593Smuzhiyun #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 27*4882a593Smuzhiyun #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 28*4882a593Smuzhiyun #define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar 29*4882a593Smuzhiyun #define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW 32*4882a593Smuzhiyun #define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter 33*4882a593Smuzhiyun #define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 34*4882a593Smuzhiyun #define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter 35*4882a593Smuzhiyun #define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE 36*4882a593Smuzhiyun #define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 37*4882a593Smuzhiyun #define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter 38*4882a593Smuzhiyun #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 39*4882a593Smuzhiyun #define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE 40*4882a593Smuzhiyun #define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW 41*4882a593Smuzhiyun #define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl 42*4882a593Smuzhiyun #define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock 43*4882a593Smuzhiyun #define REG_FPGA1_TX_INFO rFPGA1_TxInfo 44*4882a593Smuzhiyun #define REG_IQK_AGC_CONT rIQK_AGC_Cont 45*4882a593Smuzhiyun #define REG_IQK_AGC_PTS rIQK_AGC_Pts 46*4882a593Smuzhiyun #define REG_IQK_AGC_RSP rIQK_AGC_Rsp 47*4882a593Smuzhiyun #define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable 48*4882a593Smuzhiyun #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 49*4882a593Smuzhiyun #define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta 50*4882a593Smuzhiyun #define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar 51*4882a593Smuzhiyun #define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable 52*4882a593Smuzhiyun #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 53*4882a593Smuzhiyun #define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance 54*4882a593Smuzhiyun #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 55*4882a593Smuzhiyun #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 56*4882a593Smuzhiyun #define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance 57*4882a593Smuzhiyun #define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance 58*4882a593Smuzhiyun #define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE 59*4882a593Smuzhiyun #define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/ 62*4882a593Smuzhiyun #define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar 63*4882a593Smuzhiyun /*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/ 64*4882a593Smuzhiyun #define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar 65*4882a593Smuzhiyun #define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar 66*4882a593Smuzhiyun /*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/ 67*4882a593Smuzhiyun #define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar 68*4882a593Smuzhiyun /*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/ 69*4882a593Smuzhiyun #define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar 70*4882a593Smuzhiyun /*#define REG_A_TX_AGC rA_TXAGC*/ 71*4882a593Smuzhiyun #define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar 72*4882a593Smuzhiyun #define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar 73*4882a593Smuzhiyun /*#define REG_B_BBSWING rB_BBSWING*/ 74*4882a593Smuzhiyun /*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/ 75*4882a593Smuzhiyun #define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar 76*4882a593Smuzhiyun /*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/ 77*4882a593Smuzhiyun #define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar 78*4882a593Smuzhiyun /*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/ 79*4882a593Smuzhiyun #define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar 80*4882a593Smuzhiyun /*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/ 81*4882a593Smuzhiyun #define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar 82*4882a593Smuzhiyun /*#define REG_B_TX_AGC rB_TXAGC*/ 83*4882a593Smuzhiyun #define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar 84*4882a593Smuzhiyun #define REG_BLUE_TOOTH rBlue_Tooth 85*4882a593Smuzhiyun #define REG_CCK_0_AFE_SETTING rCCK0_AFESetting 86*4882a593Smuzhiyun /*#define REG_C_BBSWING rC_BBSWING*/ 87*4882a593Smuzhiyun /*#define REG_C_TX_AGC rC_TXAGC*/ 88*4882a593Smuzhiyun #define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2 89*4882a593Smuzhiyun #define REG_CONFIG_ANT_A rConfig_AntA 90*4882a593Smuzhiyun #define REG_CONFIG_ANT_B rConfig_AntB 91*4882a593Smuzhiyun #define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA 92*4882a593Smuzhiyun #define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB 93*4882a593Smuzhiyun #define REG_DPDT_CONTROL rDPDT_control 94*4882a593Smuzhiyun /*#define REG_D_BBSWING rD_BBSWING*/ 95*4882a593Smuzhiyun /*#define REG_D_TX_AGC rD_TXAGC*/ 96*4882a593Smuzhiyun #define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2 97*4882a593Smuzhiyun #define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4 98*4882a593Smuzhiyun #define REG_FPGA0_IQK rFPGA0_IQK 99*4882a593Smuzhiyun #define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction 100*4882a593Smuzhiyun #define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport 101*4882a593Smuzhiyun #define REG_FPGA0_RFMOD rFPGA0_RFMOD 102*4882a593Smuzhiyun #define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage 103*4882a593Smuzhiyun #define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW 104*4882a593Smuzhiyun #define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter 105*4882a593Smuzhiyun #define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 106*4882a593Smuzhiyun #define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter 107*4882a593Smuzhiyun #define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE 108*4882a593Smuzhiyun #define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 109*4882a593Smuzhiyun #define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter 110*4882a593Smuzhiyun #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 111*4882a593Smuzhiyun #define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE 112*4882a593Smuzhiyun #define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW 113*4882a593Smuzhiyun #define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl 114*4882a593Smuzhiyun #define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock 115*4882a593Smuzhiyun #define REG_FPGA1_TX_INFO rFPGA1_TxInfo 116*4882a593Smuzhiyun #define REG_IQK_AGC_CONT rIQK_AGC_Cont 117*4882a593Smuzhiyun #define REG_IQK_AGC_PTS rIQK_AGC_Pts 118*4882a593Smuzhiyun #define REG_IQK_AGC_RSP rIQK_AGC_Rsp 119*4882a593Smuzhiyun #define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable 120*4882a593Smuzhiyun #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 121*4882a593Smuzhiyun #define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta 122*4882a593Smuzhiyun #define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar 123*4882a593Smuzhiyun #define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable 124*4882a593Smuzhiyun #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 125*4882a593Smuzhiyun #define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance 126*4882a593Smuzhiyun #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 127*4882a593Smuzhiyun #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 128*4882a593Smuzhiyun #define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance 129*4882a593Smuzhiyun #define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance 130*4882a593Smuzhiyun #define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE 131*4882a593Smuzhiyun #define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE 132*4882a593Smuzhiyun #define REG_PMPD_ANAEN rPMPD_ANAEN 133*4882a593Smuzhiyun #define REG_PDP_ANT_A rPdp_AntA 134*4882a593Smuzhiyun #define REG_PDP_ANT_A_4 rPdp_AntA_4 135*4882a593Smuzhiyun #define REG_PDP_ANT_B rPdp_AntB 136*4882a593Smuzhiyun #define REG_PDP_ANT_B_4 rPdp_AntB_4 137*4882a593Smuzhiyun #define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar 138*4882a593Smuzhiyun #define REG_RX_CCK rRx_CCK 139*4882a593Smuzhiyun #define REG_RX_IQK rRx_IQK 140*4882a593Smuzhiyun #define REG_RX_IQK_PI_A rRx_IQK_PI_A 141*4882a593Smuzhiyun #define REG_RX_IQK_PI_B rRx_IQK_PI_B 142*4882a593Smuzhiyun #define REG_RX_IQK_TONE_A rRx_IQK_Tone_A 143*4882a593Smuzhiyun #define REG_RX_IQK_TONE_B rRx_IQK_Tone_B 144*4882a593Smuzhiyun #define REG_RX_OFDM rRx_OFDM 145*4882a593Smuzhiyun #define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2 146*4882a593Smuzhiyun #define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2 147*4882a593Smuzhiyun #define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2 148*4882a593Smuzhiyun #define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2 149*4882a593Smuzhiyun #define REG_RX_TO_RX rRx_TO_Rx 150*4882a593Smuzhiyun #define REG_RX_WAIT_CCA rRx_Wait_CCA 151*4882a593Smuzhiyun #define REG_RX_WAIT_RIFS rRx_Wait_RIFS 152*4882a593Smuzhiyun #define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch 153*4882a593Smuzhiyun /*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/ 154*4882a593Smuzhiyun #define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar 155*4882a593Smuzhiyun /*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/ 156*4882a593Smuzhiyun #define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar 157*4882a593Smuzhiyun #define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL 158*4882a593Smuzhiyun #define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar 159*4882a593Smuzhiyun #define REG_SLEEP rSleep 160*4882a593Smuzhiyun #define REG_STANDBY rStandby 161*4882a593Smuzhiyun #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar 162*4882a593Smuzhiyun #define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32 163*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar 164*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar 165*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar 166*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar 167*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar 168*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar 169*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00 170*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04 171*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08 172*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12 173*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 174*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 175*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 176*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 177*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 178*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 179*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 180*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 181*4882a593Smuzhiyun #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar 182*4882a593Smuzhiyun #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar 183*4882a593Smuzhiyun #define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06 184*4882a593Smuzhiyun #define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24 185*4882a593Smuzhiyun #define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11 186*4882a593Smuzhiyun #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar 187*4882a593Smuzhiyun #define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32 188*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar 189*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar 190*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar 191*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar 192*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar 193*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar 194*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00 195*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04 196*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08 197*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12 198*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 199*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 200*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 201*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 202*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 203*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 204*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 205*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 206*4882a593Smuzhiyun #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar 207*4882a593Smuzhiyun #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar 208*4882a593Smuzhiyun #define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06 209*4882a593Smuzhiyun #define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24 210*4882a593Smuzhiyun #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar 211*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar 212*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar 213*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar 214*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar 215*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar 216*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar 217*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 218*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 219*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 220*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 221*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 222*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 223*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 224*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 225*4882a593Smuzhiyun #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar 226*4882a593Smuzhiyun #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar 227*4882a593Smuzhiyun #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar 228*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar 229*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar 230*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar 231*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar 232*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar 233*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar 234*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 235*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 236*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 237*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 238*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 239*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 240*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 241*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 242*4882a593Smuzhiyun #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar 243*4882a593Smuzhiyun #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar 244*4882a593Smuzhiyun #define REG_TX_PATH_JAGUAR rTxPath_Jaguar 245*4882a593Smuzhiyun #define REG_TX_CCK_BBON rTx_CCK_BBON 246*4882a593Smuzhiyun #define REG_TX_CCK_RFON rTx_CCK_RFON 247*4882a593Smuzhiyun #define REG_TX_IQK rTx_IQK 248*4882a593Smuzhiyun #define REG_TX_IQK_PI_A rTx_IQK_PI_A 249*4882a593Smuzhiyun #define REG_TX_IQK_PI_B rTx_IQK_PI_B 250*4882a593Smuzhiyun #define REG_TX_IQK_TONE_A rTx_IQK_Tone_A 251*4882a593Smuzhiyun #define REG_TX_IQK_TONE_B rTx_IQK_Tone_B 252*4882a593Smuzhiyun #define REG_TX_OFDM_BBON rTx_OFDM_BBON 253*4882a593Smuzhiyun #define REG_TX_OFDM_RFON rTx_OFDM_RFON 254*4882a593Smuzhiyun #define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A 255*4882a593Smuzhiyun #define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B 256*4882a593Smuzhiyun #define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A 257*4882a593Smuzhiyun #define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B 258*4882a593Smuzhiyun #define REG_TX_TO_RX rTx_To_Rx 259*4882a593Smuzhiyun #define REG_TX_TO_TX rTx_To_Tx 260*4882a593Smuzhiyun #define REG_APK rAPK 261*4882a593Smuzhiyun #define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun #define rf_welut_jaguar RF_WeLut_Jaguar 264*4882a593Smuzhiyun #define rf_mode_table_addr RF_ModeTableAddr 265*4882a593Smuzhiyun #define rf_mode_table_data0 RF_ModeTableData0 266*4882a593Smuzhiyun #define rf_mode_table_data1 RF_ModeTableData1 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #define RX_SMOOTH_FACTOR Rx_Smooth_Factor 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun #endif /* __HAL_PHY_REG_H__ */ 271