Searched refs:MDCNFG (Results 1 – 11 of 11) sorted by relevance
137 MDCNFG |= MDCNFG_CDB2; in sa1100_update_dram_timings()145 MDCNFG = settings->mdcnfg; in sa1100_update_dram_timings()152 MDCNFG |= MDCNFG_CDB2; in sa1100_update_dram_timings()160 MDCNFG = settings->mdcnfg; in sa1100_update_dram_timings()
162 sd->mdcnfg = MDCNFG & 0x007f007f; in sdram_calculate_timing()291 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg), in sa1110_target()
139 ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG); in pxa2xx_dram_init()160 tmp |= readl(MDCNFG); in pxa2xx_dram_init()161 writelrb(tmp, MDCNFG); in pxa2xx_dram_init()
102 ldr r9, =MDCNFG130 @ Step 4 clear DE bis in MDCNFG
15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ macro
69 mdcnfg = readl_relaxed(MDCNFG); in get_sdram_rows()
73 mdcnfg = readl_relaxed(MDCNFG); in get_sdram_rows()
891 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), in __sa1111_probe()892 FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); in __sa1111_probe()
2286 #define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ macro2443 #define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ macro
1824 #define MDCNFG /* DRAM CoNFiGuration reg. */ \ macro1834 #define MDCNFG (io_p2v(_MDCNFG)) macro
1368 #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ macro