Searched hist:fbc44bd1bbbafe01848afd009d507b595b264b5f (Results 1 – 6 of 6) sorted by relevance
| /rk3399_ARM-atf/docs/components/ |
| H A D | ras.rst | fbc44bd1bbbafe01848afd009d507b595b264b5f Fri Jun 12 17:11:28 UTC 2020 Varun Wadekar <vwadekar@nvidia.com> Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch.h | fbc44bd1bbbafe01848afd009d507b595b264b5f Fri Jun 12 17:11:28 UTC 2020 Varun Wadekar <vwadekar@nvidia.com> Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | fbc44bd1bbbafe01848afd009d507b595b264b5f Fri Jun 12 17:11:28 UTC 2020 Varun Wadekar <vwadekar@nvidia.com> Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
|
| /rk3399_ARM-atf/make_helpers/ |
| H A D | defaults.mk | fbc44bd1bbbafe01848afd009d507b595b264b5f Fri Jun 12 17:11:28 UTC 2020 Varun Wadekar <vwadekar@nvidia.com> Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
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| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | build-options.rst | fbc44bd1bbbafe01848afd009d507b595b264b5f Fri Jun 12 17:11:28 UTC 2020 Varun Wadekar <vwadekar@nvidia.com> Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
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| /rk3399_ARM-atf/ |
| H A D | Makefile | fbc44bd1bbbafe01848afd009d507b595b264b5f Fri Jun 12 17:11:28 UTC 2020 Varun Wadekar <vwadekar@nvidia.com> Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
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