Merge "feat(build): enable link-time optimization by default" into integration

feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimi

feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimisations to be made across compilation unit boundaries (i.e. C
files). This is especially useful in areas with lots of closely related
compilation units that operate on the same data structures (eg PSCI and
context management).

The only drawback is that LTO makes conditions ripe for the build to
heavily mangle all functions, making debugging a nightmare. So only
enable for release builds.

Note this will make object files unintepretable by objdump. Use lto-dump
instead.

BREAKING-CHANGE: LTO has been enabled by default, which may cause
unpredictable issues for platforms where the linker scripts have not
been designed with LTO in mind. Please report any issues to the
[mailing list](mailto:tf-a@lists.trustedfirmware.org).

Change-Id: Ia472aff1a23366d918abded7a1c5da695f2c4787
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs(changelog): changelog for v2.14 release" into integration

docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind

docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3745f4506de123e3a4ff1e3ca6d5992f3b5c174a

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Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register def

Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register defines and read helpers

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feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
f

Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2
feat(per-cpu): migrate amu_ctx to per-cpu framework
feat(per-cpu): migrate spm_core_context to per-cpu framework
feat(per-cpu): migrate psci_ns_context to per-cpu framework
feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework
feat(per-cpu): migrate rmm_context to per-cpu framework
feat(per-cpu): integrate per-cpu framework into BL31/BL32
feat(per-cpu): introduce framework accessors/definers
feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework
docs(changelog): add scope for per-cpu framework

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Merge "fix(rmm): enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM" into integration

feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is de

feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is designed to minimise
cache thrashing, and the linker layout ensures each CPU’s per-cpu data
is placed on a separate cache line. This isolation is expected to
improve performance when the per-cpu framework is enabled.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie4d8b4e444971adbd9dba0446d1ab8cafaca1556

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fix(rmm): enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM

Always enable SMCCC_ARCH_FEATURE_AVAILABILITY when the
ENABLE_RME flag is set.

Change-Id: I9632d7100aace1537a931b452a9140d014871130
Signed-o

fix(rmm): enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM

Always enable SMCCC_ARCH_FEATURE_AVAILABILITY when the
ENABLE_RME flag is set.

Change-Id: I9632d7100aace1537a931b452a9140d014871130
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge changes I54152fbb,I9b70c3a2 into integration

* changes:
feat(cpufeat): introduce FEAT_RME_GDI support
feat(cpufeat): add support for FEAT_RME_GPC2

feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when en

feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when enabled, this feature enables the SA and NSP GPI encodings
by setting the corresponding bits in GPCCR_EL3.

Change-Id: I54152fbb3d19b176264e5d16acbcc866725dc290
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Timothy Hayes <timothy.hayes@arm.com>

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Merge "fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2" into integration

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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Merge changes from topic "ck/tf-a/tpip-updates" into integration

* changes:
chore(compiler-rt): update compiler-rt to v21.1.4
chore(zlib): update zlib to v1.3.1
chore(libfdt): update libfdt to

Merge changes from topic "ck/tf-a/tpip-updates" into integration

* changes:
chore(compiler-rt): update compiler-rt to v21.1.4
chore(zlib): update zlib to v1.3.1
chore(libfdt): update libfdt to v1.7.2

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chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A reposit

chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A repository. Doing so reduces the manual overhead of
updating libfdt in the future, as we avoid the need to analyse
individual source-level dependencies.

libfdt, conveniently, also provides a Makefile designed to ease its
integration into foreign build systems (like TF-A's), which we also make
use of in this change.

Source: https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/?h=v1.7.2
Change-Id: I8babcfd27019fdd6d255d550491e1bb733745f27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(security): add clrbhb support" into integration

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.

Ref- https://developer.arm.com/documentation/102898/0108/

Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "comp_build_macro" into integration

* changes:
feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT
feat(build): set CRYPTO_SUPPORT macro per BL
feat(build): create defi

Merge changes from topic "comp_build_macro" into integration

* changes:
feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT
feat(build): set CRYPTO_SUPPORT macro per BL
feat(build): create define macro to be used by BL

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Merge "feat(el3-spmc): allow physical partitions to have multiple UUIDs" into integration

feat(el3-spmc): allow physical partitions to have multiple UUIDs

Physical partitions can now be assigned multiple UUIDs. This updates
- FFA_PARTITION_INFO_GET handling to return all the required

feat(el3-spmc): allow physical partitions to have multiple UUIDs

Physical partitions can now be assigned multiple UUIDs. This updates
- FFA_PARTITION_INFO_GET handling to return all the required
parttion descriptors
- device tree parsing to read multiple UUIDs

Change-Id: Ib9a961130aace75ba31b6610873138f35d355f09
Signed-off-by: Jay Monkman <jmonkman@google.com>
Signed-off-by: Andrei Homescu <ahomescu@xwf.google.com>

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Merge "fix(build): set ERRATA_SPECULATIVE_AT after platform.mk" into integration

fix(build): set ERRATA_SPECULATIVE_AT after platform.mk

This was introduced in
289737419: fix(build): align the cpu-ops flags with all others

That patch reduced cpu-ops.mk to an elaborate defaults.

fix(build): set ERRATA_SPECULATIVE_AT after platform.mk

This was introduced in
289737419: fix(build): align the cpu-ops flags with all others

That patch reduced cpu-ops.mk to an elaborate defaults.mk and moved it
before platform.mk was evaluated. However, that patch missed the
ERRATA_SPECULATIVE_AT setting which must happen after platform.mk,
otherwise its value will not reflect errata state. So put it in the main
Makefile with other similar flag settings after platform.mk.

Change-Id: I221dab39c417531c5a148886d3e29709ba8b51a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): set CRYPTO_SUPPORT macro per BL

Moving the setting of CRYPTO_SUPPORT from the main Makefile to
individual component makefiles using the new build macro
make_defines for each BL-specific

feat(build): set CRYPTO_SUPPORT macro per BL

Moving the setting of CRYPTO_SUPPORT from the main Makefile to
individual component makefiles using the new build macro
make_defines for each BL-specific CPPFLAGS.

Rework romlib build command to use CRYPTO_LIB to determine mbedtls need
instead of CRYPTO_SUPPORT. If CRYPTO_SUPPORT is set for any component,
then CRYPTO_LIB will be filled, romlib can use this instead.

Add a convenience makefile macro for setting CRYPTO_SUPPORT from
component specific makefiles, have components call the macro based on
whether authenication verification (NEED_AUTH) and/or hash calculation
(NEED_HASH) is required for the specific boot stage.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I7e81fede74fb9c04694b022e8eebed460616565c

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Merge changes Ia8b52237,Id4b7714e into integration

* changes:
fix(build): put the -target definitions in toolchain.mk
fix(build): align the cpu-ops flags with all others