"c8284409e13ea72d08a9d858f8bcbddfb2f4df42" (history) in projects: rk3399_ARM-atf

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Searched hist:c8284409e13ea72d08a9d858f8bcbddfb2f4df42 (Results 1 – 12 of 12) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/
H A D	plat_topology.c	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
H A D	plat_zynqmp.c	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
H A D	sip_svc_setup.c	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
H A D	plat_psci.c	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
H A D	platform.mk	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
H A D	bl31_zynqmp_setup.c	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
/rk3399_ARM-atf/plat/xilinx/zynqmp/tsp/
H A D	tsp-zynqmp.mk	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
/rk3399_ARM-atf/plat/xilinx/zynqmp/include/
H A D	plat_macros.S	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
H A D	platform_def.h	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
/rk3399_ARM-atf/plat/xilinx/zynqmp/aarch64/
H A D	zynqmp_helpers.S	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
H A D	zynqmp_common.c	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A D	pm_client.c	`c8284409e13ea72d08a9d858f8bcbddfb2f4df42 Mon Mar 07 04:16:27 UTC 2016 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>`