1c8284409SSoren Brinkmann/* 2*619bc13eSMichal Simek * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved. 3c8284409SSoren Brinkmann * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5c8284409SSoren Brinkmann */ 6c8284409SSoren Brinkmann 7c8284409SSoren Brinkmann#include <asm_macros.S> 809d40e0eSAntonio Nino Diaz#include <drivers/arm/gicv2.h> 9c8284409SSoren Brinkmann#include <platform_def.h> 10c8284409SSoren Brinkmann 11c8284409SSoren Brinkmann .globl plat_secondary_cold_boot_setup 12c8284409SSoren Brinkmann .globl plat_is_my_cpu_primary 13bde25ae2SAntonio Nino Diaz .globl zynqmp_calc_core_pos 14bde25ae2SAntonio Nino Diaz .globl plat_my_core_pos 15bde25ae2SAntonio Nino Diaz .globl platform_mem_init 16c8284409SSoren Brinkmann 17c8284409SSoren Brinkmann /* ----------------------------------------------------- 18c8284409SSoren Brinkmann * void plat_secondary_cold_boot_setup (void); 19c8284409SSoren Brinkmann * 20c8284409SSoren Brinkmann * This function performs any platform specific actions 21c8284409SSoren Brinkmann * needed for a secondary cpu after a cold reset e.g 22c8284409SSoren Brinkmann * mark the cpu's presence, mechanism to place it in a 23c8284409SSoren Brinkmann * holding pen etc. 24c8284409SSoren Brinkmann * TODO: Should we read the PSYS register to make sure 25c8284409SSoren Brinkmann * that the request has gone through. 26c8284409SSoren Brinkmann * ----------------------------------------------------- 27c8284409SSoren Brinkmann */ 28c8284409SSoren Brinkmannfunc plat_secondary_cold_boot_setup 29c8284409SSoren Brinkmann mrs x0, mpidr_el1 30c8284409SSoren Brinkmann 31c8284409SSoren Brinkmann /* Deactivate the gic cpu interface */ 32c8284409SSoren Brinkmann ldr x1, =BASE_GICC_BASE 33c8284409SSoren Brinkmann mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) 34c8284409SSoren Brinkmann orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) 35c8284409SSoren Brinkmann str w0, [x1, #GICC_CTLR] 36c8284409SSoren Brinkmann 37c8284409SSoren Brinkmann /* 38c8284409SSoren Brinkmann * There is no sane reason to come out of this wfi. This 39c8284409SSoren Brinkmann * cpu will be powered on and reset by the cpu_on pm api 40c8284409SSoren Brinkmann */ 41c8284409SSoren Brinkmann dsb sy 42c8284409SSoren Brinkmann1: 43a806dad5SJeenu Viswambharan no_ret plat_panic_handler 44c8284409SSoren Brinkmannendfunc plat_secondary_cold_boot_setup 45c8284409SSoren Brinkmann 46c8284409SSoren Brinkmannfunc plat_is_my_cpu_primary 47c8284409SSoren Brinkmann mov x9, x30 48c8284409SSoren Brinkmann bl plat_my_core_pos 49c8284409SSoren Brinkmann cmp x0, #ZYNQMP_PRIMARY_CPU 50c8284409SSoren Brinkmann cset x0, eq 51c8284409SSoren Brinkmann ret x9 52c8284409SSoren Brinkmannendfunc plat_is_my_cpu_primary 53bde25ae2SAntonio Nino Diaz 54bde25ae2SAntonio Nino Diaz /* ----------------------------------------------------- 55bde25ae2SAntonio Nino Diaz * unsigned int plat_my_core_pos(void) 56bde25ae2SAntonio Nino Diaz * This function uses the zynqmp_calc_core_pos() 57bde25ae2SAntonio Nino Diaz * definition to get the index of the calling CPU. 58bde25ae2SAntonio Nino Diaz * ----------------------------------------------------- 59bde25ae2SAntonio Nino Diaz */ 60bde25ae2SAntonio Nino Diazfunc plat_my_core_pos 61bde25ae2SAntonio Nino Diaz mrs x0, mpidr_el1 62bde25ae2SAntonio Nino Diaz b zynqmp_calc_core_pos 63bde25ae2SAntonio Nino Diazendfunc plat_my_core_pos 64bde25ae2SAntonio Nino Diaz 65bde25ae2SAntonio Nino Diaz /* ----------------------------------------------------- 66bde25ae2SAntonio Nino Diaz * unsigned int zynqmp_calc_core_pos(u_register_t mpidr) 67bde25ae2SAntonio Nino Diaz * Helper function to calculate the core position. 68bde25ae2SAntonio Nino Diaz * With this function: CorePos = (ClusterId * 4) + 69bde25ae2SAntonio Nino Diaz * CoreId 70bde25ae2SAntonio Nino Diaz * ----------------------------------------------------- 71bde25ae2SAntonio Nino Diaz */ 72bde25ae2SAntonio Nino Diazfunc zynqmp_calc_core_pos 73bde25ae2SAntonio Nino Diaz and x1, x0, #MPIDR_CPU_MASK 74bde25ae2SAntonio Nino Diaz and x0, x0, #MPIDR_CLUSTER_MASK 75bde25ae2SAntonio Nino Diaz add x0, x1, x0, LSR #6 76bde25ae2SAntonio Nino Diaz ret 77bde25ae2SAntonio Nino Diazendfunc zynqmp_calc_core_pos 78bde25ae2SAntonio Nino Diaz 79bde25ae2SAntonio Nino Diaz /* --------------------------------------------------------------------- 80bde25ae2SAntonio Nino Diaz * We don't need to carry out any memory initialization on ARM 81bde25ae2SAntonio Nino Diaz * platforms. The Secure RAM is accessible straight away. 82bde25ae2SAntonio Nino Diaz * --------------------------------------------------------------------- 83bde25ae2SAntonio Nino Diaz */ 84bde25ae2SAntonio Nino Diazfunc platform_mem_init 85bde25ae2SAntonio Nino Diaz ret 86bde25ae2SAntonio Nino Diazendfunc platform_mem_init 87