Searched hist:af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | immap_lsch2.h | af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e Wed Nov 11 09:58:34 UTC 2015 Mingkai Hu <Mingkai.Hu@freescale.com> pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | immap_lsch3.h | af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e Wed Nov 11 09:58:34 UTC 2015 Mingkai Hu <Mingkai.Hu@freescale.com> pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
| H A D | soc.h | af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e Wed Nov 11 09:58:34 UTC 2015 Mingkai Hu <Mingkai.Hu@freescale.com> pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
| H A D | config.h | af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e Wed Nov 11 09:58:34 UTC 2015 Mingkai Hu <Mingkai.Hu@freescale.com> pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/drivers/pci/ |
| H A D | pcie_layerscape.c | af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e Wed Nov 11 09:58:34 UTC 2015 Mingkai Hu <Mingkai.Hu@freescale.com> pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|