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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
[all …]
H A Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
H A Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.50a
25 - snps,dwmac-3.610
26 - snps,dwmac-3.70a
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 of common properties between various SOC designs. It thus enables us to use
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/net/
H A Dstmmac.txt4 - compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac"
5 For backwards compatibility: "st,spear600-gmac" is also supported.
6 - reg: Address and length of the register set for the device
7 - interrupt-parent: Should be the phandle for the interrupt controller
9 - interrupts: Should contain the STMMAC interrupts
10 - interrupt-names: Should contain the interrupt names "macirq"
13 - phy-mode: See ethernet.txt file in the same directory.
14 - snps,reset-gpio gpio number for phy reset.
15 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
16 - snps,reset-delays-us is triplet of delays
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
39 /* Soft Reset register masks */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
45 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-bcmcygnus/
H A Dconfigs.h2 * Copyright 2014-2017 Broadcom.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/iproc-common/configs.h>
15 /* Post pad 3 bytes after each reg addr */
16 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
27 #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
/OK3568_Linux_fs/kernel/drivers/w1/
H A Dw1_io.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/delay.h>
48 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
50 * @bit: 0 - write a 0, 1 - write a 0 read the level
54 if (dev->bus_master->touch_bit) in w1_touch_bit()
55 return dev->bus_master->touch_bit(dev->bus_master->data, bit); in w1_touch_bit()
66 * w1_write_bit() - Generates a write-0 or write-1 cycle.
70 * Only call if dev->bus_master->touch_bit is NULL
79 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit()
81 dev->bus_master->write_bit(dev->bus_master->data, 1); in w1_write_bit()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6qdl-apf6.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 reg_1p8v: regulator-1p8v {
10 compatible = "regulator-fixed";
11 regulator-name = "1P8V";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <1800000>;
14 regulator-always-on;
15 vin-supply = <&reg_3p3v>;
[all …]
H A Dsun8i-s3-pinecube.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
6 /dts-v1/;
7 #include "sun8i-v3.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
38 compatible = "regulator-fixed";
39 regulator-name = "vcc5v0";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h4 * SPDX-License-Identifier: GPL-2.0+
30 * register. As such, the U-Boot clock driver is currently a bit lazy, and
40 #include <asm/arch/clock-tables.h>
41 /* PLL stabilization delay in usec */
56 * @param divp post divider 2^n
60 * @returns monotonic time in us that the PLL will be stable
72 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
78 * Read low-level parameters of a PLL.
83 * @param divp returns post divider 2^n
87 * @returns 0 if ok, -1 on error (invalid clock id)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5-nanopi-neo-plus2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
6 #include "sun50i-h5.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/pinctrl/sun4i-a10.h>
14 compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
22 stdout-path = "serial0:115200n8";
26 compatible = "gpio-leds";
31 default-state = "on";
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588-vehicle-evb-v21.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "dt-bindings/usb/pd.h"
9 #include "rk3588-vehicle-v20.dtsi"
10 #include "rk3588-rk806-dual.dtsi"
12 pcie20_avdd0v85: pcie20-avdd0v85 {
13 compatible = "regulator-fixed";
14 regulator-name = "pcie20_avdd0v85";
15 regulator-boot-on;
16 regulator-always-on;
17 regulator-min-microvolt = <850000>;
[all …]
H A Drk3562-evb2-ddr4-v10.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
10 #include "rk3562-evb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/sensor-dev.h>
17 compatible = "rockchip,rk3562-evb2-ddr4-v10", "rockchip,rk3562";
19 dc_12v: dc-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "dc_12v";
[all …]
H A Drk3562-evb1-lp4x-v10.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "dt-bindings/usb/pd.h"
11 #include "rk3562-evb.dtsi"
12 #include "rk3562-evb1-cam.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pinctrl/rockchip.h>
15 #include <dt-bindings/sensor-dev.h>
19 compatible = "rockchip,rk3562-evb1-lp4x-v10", "rockchip,rk3562";
21 dc_12v: dc-12v {
[all …]
H A Drk3562-test1-ddr3-v10.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
10 #include "rk3562-evb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
16 compatible = "rockchip,rk3562-test1-ddr3-v10", "rockchip,rk3562";
18 dc_12v: dc-12v {
19 compatible = "regulator-fixed";
20 regulator-name = "dc_12v";
21 regulator-always-on;
[all …]
H A Drk3588-evb2-lp4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "rk3588-evb.dtsi"
9 #include "rk3588-rk806-dual.dtsi"
12 es7202_sound_micarray: es7202-sound-micarray {
14 compatible = "simple-audio-card";
15 simple-audio-card,format = "i2s";
16 simple-audio-card,name = "rockchip,sound-micarray";
17 simple-audio-card,mclk-fs = <256>;
18 simple-audio-card,dai-link@0 {
21 sound-dai = <&pdm0>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/
H A Dcu1830-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,tcu.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1830-neo", "ingenic,x1830";
11 model = "YSH & ATIL General Board CU1830-Neo";
18 stdout-path = "serial1:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]
H A Dcu1000-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,tcu.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1000-neo", "ingenic,x1000e";
11 model = "YSH & ATIL General Board CU1000-Neo";
18 stdout-path = "serial2:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dsram243x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram243x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
H A Dsram242x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram242x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/core/
H A Dpwrseq_simple.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/delay.h>
39 struct gpio_descs *reset_gpios = pwrseq->reset_gpios; in mmc_pwrseq_simple_set_gpios_value()
43 int nvalues = reset_gpios->ndescs; in mmc_pwrseq_simple_set_gpios_value()
54 gpiod_set_array_value_cansleep(nvalues, reset_gpios->desc, in mmc_pwrseq_simple_set_gpios_value()
55 reset_gpios->info, values); in mmc_pwrseq_simple_set_gpios_value()
63 struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); in mmc_pwrseq_simple_pre_power_on()
65 if (!IS_ERR(pwrseq->ext_clk) && !pwrseq->clk_enabled) { in mmc_pwrseq_simple_pre_power_on()
66 clk_prepare_enable(pwrseq->ext_clk); in mmc_pwrseq_simple_pre_power_on()
67 pwrseq->clk_enabled = true; in mmc_pwrseq_simple_pre_power_on()
[all …]
/OK3568_Linux_fs/kernel/Documentation/admin-guide/blockdev/
H A Dparide.rst5 PARIDE v1.03 (c) 1997-8 Grant Guenther <grant@torque.net>
11 to personal computers, many external devices such as portable hard-disk,
12 CD-ROM, LS-120 and tape drives use the parallel port to connect to their
13 host computer. While some devices (notably scanners) use ad-hoc methods
16 a parallel-port adapter chip added in. Some of the original parallel port
18 (The Iomega PPA-3 adapter used in the ZIP drives is an example of this
26 which is then connected to a floppy-tape mechanism. The vast majority
29 were to open up a parallel port CD-ROM drive, for instance, one would
30 find a standard ATAPI CD-ROM drive, a power supply, and a single adapter
32 IDE cable. It is usually possible to exchange the CD-ROM device with
[all …]

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