1*4882a593SmuzhiyunHisilicon hix5hd2 gmac controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should contain one of the following SoC strings: 5*4882a593Smuzhiyun * "hisilicon,hix5hd2-gmac" 6*4882a593Smuzhiyun * "hisilicon,hi3798cv200-gmac" 7*4882a593Smuzhiyun * "hisilicon,hi3516a-gmac" 8*4882a593Smuzhiyun and one of the following version string: 9*4882a593Smuzhiyun * "hisilicon,hisi-gmac-v1" 10*4882a593Smuzhiyun * "hisilicon,hisi-gmac-v2" 11*4882a593Smuzhiyun The version v1 includes SoCs hix5hd2. 12*4882a593Smuzhiyun The version v2 includes SoCs hi3798cv200, hi3516a. 13*4882a593Smuzhiyun- reg: specifies base physical address(s) and size of the device registers. 14*4882a593Smuzhiyun The first region is the MAC register base and size. 15*4882a593Smuzhiyun The second region is external interface control register. 16*4882a593Smuzhiyun- interrupts: should contain the MAC interrupt. 17*4882a593Smuzhiyun- #address-cells: must be <1>. 18*4882a593Smuzhiyun- #size-cells: must be <0>. 19*4882a593Smuzhiyun- phy-mode: see ethernet.txt [1]. 20*4882a593Smuzhiyun- phy-handle: see ethernet.txt [1]. 21*4882a593Smuzhiyun- clocks: clock phandle and specifier pair. 22*4882a593Smuzhiyun- clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional). 23*4882a593Smuzhiyun- resets: should contain the phandle to the MAC core reset signal(optional), 24*4882a593Smuzhiyun the MAC interface reset signal(optional) 25*4882a593Smuzhiyun and the PHY reset signal(optional). 26*4882a593Smuzhiyun- reset-names: contain the reset signal name "mac_core"(optional), 27*4882a593Smuzhiyun "mac_ifc"(optional) and "phy"(optional). 28*4882a593Smuzhiyun- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given. 29*4882a593Smuzhiyun The 1st cell is reset pre-delay in micro seconds. 30*4882a593Smuzhiyun The 2nd cell is reset pulse in micro seconds. 31*4882a593Smuzhiyun The 3rd cell is reset post-delay in micro seconds. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunThe MAC address will be determined using the properties defined in 34*4882a593Smuzhiyunethernet.txt[1]. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- PHY subnode: inherits from phy binding [2] 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/net/ethernet.txt 39*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/net/phy.txt 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExample: 42*4882a593Smuzhiyun gmac0: ethernet@f9840000 { 43*4882a593Smuzhiyun compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 44*4882a593Smuzhiyun reg = <0xf9840000 0x1000>,<0xf984300c 0x4>; 45*4882a593Smuzhiyun interrupts = <0 71 4>; 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <0>; 48*4882a593Smuzhiyun phy-mode = "rgmii"; 49*4882a593Smuzhiyun phy-handle = <&phy2>; 50*4882a593Smuzhiyun mac-address = [00 00 00 00 00 00]; 51*4882a593Smuzhiyun clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>; 52*4882a593Smuzhiyun clock-names = "mac_core", "mac_ifc"; 53*4882a593Smuzhiyun resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>; 54*4882a593Smuzhiyun reset-names = "mac_core", "mac_ifc", "phy"; 55*4882a593Smuzhiyun hisilicon,phy-reset-delays-us = <10000 10000 30000>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun phy2: ethernet-phy@2 { 58*4882a593Smuzhiyun reg = <2>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61