xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6qdl-apf6.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2015 Armadeus Systems <support@armadeus.com>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
6*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	reg_1p8v: regulator-1p8v {
10*4882a593Smuzhiyun		compatible = "regulator-fixed";
11*4882a593Smuzhiyun		regulator-name = "1P8V";
12*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
13*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
14*4882a593Smuzhiyun		regulator-always-on;
15*4882a593Smuzhiyun		vin-supply = <&reg_3p3v>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	usdhc1_pwrseq: usdhc1-pwrseq {
19*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
20*4882a593Smuzhiyun		reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
21*4882a593Smuzhiyun		post-power-on-delay-ms = <15>;
22*4882a593Smuzhiyun		power-off-delay-us = <70>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun&fec {
27*4882a593Smuzhiyun	pinctrl-names = "default";
28*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
29*4882a593Smuzhiyun	phy-mode = "rgmii-id";
30*4882a593Smuzhiyun	phy-reset-duration = <10>;
31*4882a593Smuzhiyun	phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
32*4882a593Smuzhiyun	phy-handle = <&ethphy1>;
33*4882a593Smuzhiyun	status = "okay";
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	mdio {
36*4882a593Smuzhiyun		#address-cells = <1>;
37*4882a593Smuzhiyun		#size-cells = <0>;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		ethphy1: ethernet-phy@1 {
40*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
41*4882a593Smuzhiyun			reg = <1>;
42*4882a593Smuzhiyun			interrupt-parent = <&gpio1>;
43*4882a593Smuzhiyun			interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
44*4882a593Smuzhiyun			status = "okay";
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun/* Bluetooth */
50*4882a593Smuzhiyun&uart2 {
51*4882a593Smuzhiyun	pinctrl-names = "default";
52*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
53*4882a593Smuzhiyun	uart-has-rtscts;
54*4882a593Smuzhiyun	status = "okay";
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun/* Wi-Fi */
58*4882a593Smuzhiyun&usdhc1 {
59*4882a593Smuzhiyun	pinctrl-names = "default";
60*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
61*4882a593Smuzhiyun	bus-width = <4>;
62*4882a593Smuzhiyun	mmc-pwrseq = <&usdhc1_pwrseq>;
63*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
64*4882a593Smuzhiyun	vqmmc-supply = <&reg_1p8v>;
65*4882a593Smuzhiyun	cap-power-off-card;
66*4882a593Smuzhiyun	keep-power-in-suspend;
67*4882a593Smuzhiyun	non-removable;
68*4882a593Smuzhiyun	status = "okay";
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	#address-cells = <1>;
71*4882a593Smuzhiyun	#size-cells = <0>;
72*4882a593Smuzhiyun	wlcore: wlcore@2 {
73*4882a593Smuzhiyun		compatible = "ti,wl1271";
74*4882a593Smuzhiyun		reg = <2>;
75*4882a593Smuzhiyun		interrupt-parent = <&gpio2>;
76*4882a593Smuzhiyun		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
77*4882a593Smuzhiyun		ref-clock-frequency = <38400000>;
78*4882a593Smuzhiyun		tcxo-clock-frequency = <38400000>;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun/* eMMC */
83*4882a593Smuzhiyun&usdhc3 {
84*4882a593Smuzhiyun	pinctrl-names = "default";
85*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
86*4882a593Smuzhiyun	bus-width = <8>;
87*4882a593Smuzhiyun	no-1-8-v;
88*4882a593Smuzhiyun	non-removable;
89*4882a593Smuzhiyun	status = "okay";
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun&iomuxc {
93*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
94*4882a593Smuzhiyun		fsl,pins = <
95*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
96*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
97*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
98*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24	0x130b0
99*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x130b0
100*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
101*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
102*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
103*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
104*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
105*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
106*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x13030
107*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
108*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
109*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1f030
110*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1f030
111*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
112*4882a593Smuzhiyun		>;
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
116*4882a593Smuzhiyun		fsl,pins = <
117*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b0
118*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b0
119*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b0
120*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b0
121*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x130b0 /* BT_EN */
122*4882a593Smuzhiyun		>;
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
126*4882a593Smuzhiyun		fsl,pins = <
127*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17059
128*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10059
129*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17059
130*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17059
131*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17059
132*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17059
133*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT0__GPIO2_IO08	0x130b0 /* WL_EN */
134*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10	0x130b0 /* WL_IRQ */
135*4882a593Smuzhiyun		>;
136*4882a593Smuzhiyun	};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3grp {
139*4882a593Smuzhiyun		fsl,pins = <
140*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
141*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
142*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
143*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
144*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
145*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
146*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
147*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
148*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
149*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
150*4882a593Smuzhiyun		>;
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun};
153